mc33912 Freescale Semiconductor, Inc, mc33912 Datasheet - Page 40

• Manufacturer Part Number: mc33912
• Description: Lin System Basis Chip With Dc Motor Pre-driver And Current Sense
• Manufacturer: Freescale Semiconductor, Inc

Timing Control Register - TIMCR
configure the watchdog and the cyclic sense periods. Writing
to the Timing Control Register (TIMCR) will also return the
Watchdog Status Register (WDSR).
CS/WD - Cyclic Sense or Watchdog prescaler select
to, the Cyclic Sense prescaler or the Watchdog prescaler.
WDx - Watchdog Prescaler
prescaler and therefore selects the watchdog period in
accordance with
windowing watchdog is active.
Table 22. watchdog Prescaler
CYSTx - Cyclic Sense Period Prescaler Select
cyclic sensing together with the bit CYSX8 in the
Configuration Register (CFR) (see page 41).
40
33912
FUNCTIONAL DEVICE OPERATIONS
LOGIC COMMANDS AND REGISTERS
WD2
This register is a double purpose register which allows to
This write-only bit selects which prescaler is being written
1 = Cyclic Sense Prescaler selected
0 = Watchdog Prescaler select
This write-only bits selects the divider for the watchdog
This write-only bits selects the interval for the wake-up
Table 21. Timing Control Register - $A
0
0
0
0
1
1
1
1
Condition
Reset
Value
Reset
Write
WD1
0
0
1
1
0
0
1
1
CS/WD
Table
C3
-
-
WD0
0
1
0
1
0
1
0
1
22. This configuration is valid only if
CYST2
WD2
C2
0
Prescaler Divider
CYST1
WD1
POR
C1
0
10
12
14
1
2
4
6
8
CYST0
WD0
C0
0
enabled when entering in Stop or Sleep Mode. Otherwise a
timed wake-up is performed after the period shown in
Table
Table 23. Cyclic Sense Interval
Watchdog Status Register - WDSR
is also returned when writing to the TIMCR.
WDTO - Watchdog Timeout
either a watchdog timeout or by an attempt to clear the
Watchdog within the window closed.
(TIMCR) will clear the WDTO bit.
Notes
CYSX8
60.
This option is only active if one of the high side switches is
This register returns the Watchdog status information and
This read-only bit signals the last reset was caused by
Any access to this register or the Timing Control Register
1 = Last reset caused by watchdog timeout
0 = None
X
0
0
0
0
0
0
0
1
1
1
1
1
1
1
23.
bit CYSX8 is located in Configuration Register (CFR)
(60)
Table 24. Watchdog Status Register - $A/$B
Read
CYST2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
WDTO
S3
CYST1
Analog Integrated Circuit Device Data
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
WDERR
S2
CYST0
Freescale Semiconductor
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
WDOFF
S1
No cyclic sense
WDWO
Interval
1120ms
S0
100ms
120ms
140ms
160ms
320ms
480ms
640ms
800ms
960ms
20ms
40ms
60ms
80ms