mc33984 Freescale Semiconductor, Inc, mc33984 Datasheet - Page 23

• Manufacturer Part Number: mc33984
• Description: Dual Intelligent High-current Self-protected Silicon High-side Switch 4.0 M
• Manufacturer: Freescale Semiconductor, Inc

DEVICE REGISTER ADDRESSING
addresses and their impact on device operation.
Address x000 — Status Register (STATR)
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D2:D0, determine the content of the first eight bits of SO data.
When register content is specific to one of the two outputs, bit
D7 is used to select the desired output (SOA3). In addition to
the device status, this feature provides the ability to read the
content of the OCR, SOCHLR, CDTOLR, DICR, OSDR,
WDR, NAR, and UOVR registers. (Refer to the section
entitled
Data).)
Address x001 — Output Control Register (OCR)
through the SPI. Incoming message bit D0 reflects the
desired states of the high-side output HS0 (IN0_SPI): a
Logic [1] enables the output switch and a Logic [0] turns it
OFF. A Logic [1] on message bit D1 enables the Current
Sense (CSNS) pin. Similarly, incoming message bit D2
reflects the desired states of the high-side output HS1
(IN1_SPI): Logic [1] enables the output switch and a Logic [0]
turns it OFF. A Logic [1] on message bit D3 enables the
CSNS pin. In the event that the current sense is enabled for
both outputs, the current will be summed. Bit D7 is used to
feed the watchdog if enabled.
Address x010— Select Overcurrent High and Low
Register (SOCHLR)
output overcurrent low and high detection levels,
respectively. Each output is independently selected for
configuration based on the state of the D7 bit; a write to this
register when D7 is Logic [0] will configure the current
detection levels for the HS0. Similarly, if D7 is Logic [1] when
this register is written, HS1 is configured. Each output can be
configured to different levels. In addition to protecting the
device, this slow blow fuse emulation feature can be used to
optimize the load requirements matching system
characteristics. Bits D2 : D0 set the overcurrent low detection
level to one of eight possible levels, as shown in
Bit D3 sets the overcurrent high detection level to one of two
levels, which is described
Analog Integrated Circuit Device Data
Freescale Semiconductor
The following section describes the possible register
The STATR register is used to read the device status and
The OCR register allows the MCU to control the outputs
The SOCHLR register allows the MCU to configure the
Serial Output Communication (Device Status Return
inTable 11.
Table
10.
Table 12. Overcurrent Low Detection Blanking Time
Table 10. Overcurrent Low Detection Levels
Table 11. Overcurrent High Detection Levels
Address x011 — Current Detection Time and Open Load
Register (CDTOLR)
the amount of time the device will allow an overcurrent low
condition before output latches OFF occurs. Each output is
independently selected for configuration based on the state
of the D7 bit. A write to this register when bit 7 is Logic [0] will
configure the timeout for the HS0. Similarly, if D7 is Logic [1]
when this register is written, then HS1 is configured. Bits
D1: D0 allow the MCU to select one of four fault blanking
times defined in
only to the overcurrent low detection levels. If the selected
overcurrent high level is reached, the device will latch off
within 20
detection timeout feature. A Logic [1] on bit D3 disables the
open load (OL) detection feature.
SOCL2
The CDTOLR register is used by the MCU to determine
A Logic [1] on bit D2 disables the overcurrent low (CD_dis)
(D2)
0
0
0
0
1
1
1
1
SOCH (D3)
OCLT [1:0]
µ
s
.
SOCL1
00
01
10
11
0
1
(D1)
0
0
1
1
0
0
1
1
Table
SOCL0
12. Note that these time-outs apply
LOGIC COMMANDS AND REGISTERS
(D0)
0
1
0
1
0
1
0
1
FUNCTIONAL DEVICE OPERATION
Overcurrent High Detection
Overcurrent Low Detection
(Amperes)
155 ms
(Amperes)
150 µ s
Timing
1.2 ms
10 ms
100
75
22.5
17.5
12.5
7.5
25
20
15
10
33984
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