mc33091ap Freescale Semiconductor, Inc, mc33091ap Datasheet - Page 11

• Manufacturer Part Number: mc33091ap
• Description: High-side Tmos Driver
• Manufacturer: Freescale Semiconductor, Inc

will normally reveal the current value, I DS(max) , to be
expected under a dead short condition. TMOS data sheets
normally depict graphs of drain current versus drain to source
voltage for various gate to source voltages from which the
drain current at 7.0 V V GS , I DS(max) , can reasonably be
approximated. Using this information, the peak TMOS power
dissipation under a dead short condition is approximated
to be:
multiplied by the duty cycle (DC):
the maximum power dissipation of the TMOS device under
normal conditions, the short circuit protection scheme of the
MC33091A will adequately protect the TMOS device. The
duty cycle at which the MC33091A controls the gate can be
determined by using Figure 30.
the sensed V DS voltage developed across the TMOS device
and R X in accordance with Equations 1 and 2. At the onset of
an overload condition, the voltage across C T will be less than
the V TH threshold voltage of the upper comparator with the
TMOS device in an “on” state. I SQ current will increase
dramatically and the timing capacitor C T charges toward V TH .
When the voltage on C T reaches the V TH threshold voltage of
the upper comparator, the upper comparator output goes
high setting the latch output (Q) high, turning on the open
collector NPN transistor and pulling the Fault output low. At
MOTOROLA ANALOG IC DEVICE DATA
The data sheet for the particular TMOS device being used
The average power is equal to the peak power dissipation
As long as the average power, in Equation 9, is less than
As previously discussed, I SQ is externally dependant on
8.0
6.0
4.0
2.0
10
0
2.0
P D(peak) = V S(max) I DS(max)
Figure 30. MC33091A Duty Cycle
4.0
P D(avg) = P D(peak) DC
versus V DS / V DS(min)
6.0
V DS /V DS(min)
DC =
1 +
In
(V TH – 2 V TH )
(V TL – 2 V TH )
In(V TL /V TH )
8.0
1
V TH = 4.6 V
V TL = 0.95 V
= V DS /V DS(min)
10
MC33091A
12
(8)
(9)
the same time, I SQ is switched off, allowing C T to discharge
through resistor R T to V TL , at which time the TMOS device is
again switched on. This action is repeated so long as the
overload condition exists. The V TL and V TH thresholds are
internally set to approximately 0.95 V and 4.6 V respectively.
charge plus discharge time and represented by:
DC = 1/1+ln(V TL /V TH )/ln{(V TH – 2 V TH )/(V TL – 2 V TH )} (13)
drain to source voltage, V DS , of the TMOS device to the
minimum drain to source voltage, V DS(min) , allowing
uninterrupted continuous TMOS operation as calculated in
Equation 5. A graph of Equation 13 is shown in Figure 30 and
is valid for any ratio of V DS to V DS(min) . Knowing this ratio, the
duty cycle can be determined by using Figure 30 or Equation
13 and knowing the duty cycle, the average power
dissipation can be calculated by using Equation 9.
ground a minimum duty cycle will be experienced which can
be calculated. When this condition exists, the TMOS device
experiences a V DS voltage of V S which is sensed by the
MC33091A. The MC33091A very rapidly charges the timing
capacitor C T to V TH shutting down the TMOS device. This
condition produces the minimum duty cycle for the specific
system conditions. The minimum duty cycle can be
calculated for any valid V S voltage by substituting the value of
V S used for V DS in Equation 13 and solving for the duty cycle.
determination of the average power as was pointed out in
Equation 9. TMOS data sheets specify the maximum
allowable junction temperature and thermal resistance,
junction–to–case, at which the device may be operated.
Knowing the average power and the device thermal
information, proper heatsinking of the TMOS device can
be determined.
V DS(min) produce shorter duty cycles, for given V DS voltages.
The minimum duty cycle, being limited to the case where
V DS = V S , increases as higher values of V S are used.
The charge time (t c ) of C T can be shown as:
The discharge time (t d ) of C T can be shown as:
The duty cycle is defined as charge time divided by the
Substituting Equations 10 and 11 into 12:
Notice the duty cycle is dependent only on the ratio of the
If the TMOS device experiences a hard load short to
Knowing the duty cycle and peak power allows
The duty cycle graph (Figure 30) reveals lower values of
t c = –R T C T ln[1–(V TH –V TL )/(I SQ R T –V TL )]
where: = V DS /V DS(min)
t d = –R T C T ln(V TL /V TH )
DC = t c /(t c +t d )
11
(10)
(12)
(11)