adv611-adv612 Analog Devices, Inc., adv611-adv612 Datasheet

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... ADV611/ADV612 offer many application-specific advantages. A review of the General Theory of Operation and Applying the ADV611/ADV612 sections will help you get the most use out of the ADV611/ADV612 in any given application. The ADV611/ADV612 accept component digital video through the Video Interface and outputs a compressed bitstream though the Host Interface in Encode Mode ...

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... Host Interface (Indirect Address, Indirect Register Data, and Interrupt Mask/Status) Register Timing . . . . . . . . . . . 40 Host Interface (Compressed Data) Register Timing . . . . . . . 42 ADV611/ADV612 LQFP PINOUTS . . . . . . . . . . . . . . . . . . . . 44 ADV611/ADV612 PIN CONFIGURATION . . . . . . . . . . . . . . 45 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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... The background contrast level is controlled by the user. The lower the contrast level, the more the image will be compressed. The objective in a given Table II. Differences Between the ADV601, ADV601LC, ADV611 and ADV612 ADV601 Bits per Component 10 ...

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... This is a 5-bit register that allows fields to be “skipped.” Stall Mode It is possible to stall or halt the ADV611/ADV612 at any time during Encode Mode. This allows the user to feed uncompressed video data to these parts and to stop indefinitely between fields or even between pixels ...

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... Through leverage of these key points, the ADV611/ADV612 not only compresses video, but offers a host of application features. Please see the Applying the ADV611/ADV612 section for details on getting the most out of the ADV611/ADV612’s subband coding architecture in different applications BLOCK H IS HIGH PASS IN X, HIGH PASS IN Y, AND DECIMATED BY 128. ...

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... ADV611/ADV612 Figure 6. Unfiltered Original Image (Analog Devices Corporate Offices, Norwood, Massachusetts) Figure 7. Modified Mallat Diagram of Image –6– REV. 0 ...

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... HIGH PASS IN BLOCK BLOCK BLOCK HIGH LOW PASS IN PASS BLOCK BLOCK K Figure 8. Wavelet Filter Tree Structure –7– ADV611/ADV612 STAGE 1 STAGE 2 STAGE 3 STAGE 4 Y LOW PASS STAGE 5 HIGH LOW PASS IN PASS ...

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... Mallat block data and (2) levels of quantization range widely from high to low frequency block. (Note that the fill is based on a log formula.) The relation between actual ADV611/ADV612 bin width factors and the Mallat block fill pattern in Figure 10 appears in Table III ...

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... PROGRAMMER’S MODEL 0x0054 A host device configures the ADV611/ADV612 using the Host 0x0054 I/O Port. The host reads from status registers and writes to 0x0054 control registers through the Host I/O Port. 0x0054 0x0046 Table V ...

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... INDIRECT REGISTER ADDRESS AND INDIRECT REGISTER DATA REGISTERS} *NOTE: YOU MUST WRITE 0X0880 TO THE MODE CONTROL REGISTER ON CHIP RESET TO SELECT THE CORRECT PIXEL MODE Figure 11. Map of ADV611/ADV612 Direct and Indirect Registers DIRECT (EXTERNALLY ACCESSIBLE) REGISTERS BYTE 2 BYTE 1 RESERVED INDIRECT REGISTER ADDRESS ...

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... Interrupt Mask / Status Register Direct (Read/Write) Register Byte Offset 0x0C This 16-bit register contains interrupt mask and status bits that control the state of the ADV611/ADV612’s HIRQ pin. With the seven mask bits (IE_LCODE, IE_STATSR, IE_FIFOSTP, IE_FIFOSRQ, IE_FIFOERR, IE_CCIRER, IE_MERR), select the con- ditions that are ORed together to determine the output of the HIRQ pin ...

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... Memory Error, MERR. This condition indicates that an error has occurred at the DRAM memory interface. This condition can be caused by a defective DRAM, the inability of the Host to keep up with the ADV611/ADV612 compressed data stream, or bit errors in the data stream. Note that the ADV611/ADV612 recovers from this condition without host intervention. ...

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... Because each register is four bits in size, and the FIFO is 512 positions, the 4-bit value must be multiplied by 32 (decimal) to determine the exact value for encode service level (nearly full) and decode service level (nearly empty). The ADV611/ADV612 uses these settings to determine when to generate a FIFO Service Request related host interrupt (FIFOSRQ bit and FIFO_SRQ pin). ...

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... Indirect (Write Only) Register Index 0x05 This register holds the setting for the vertical end of the ADV611/ADV612’s active video area or quality box. If the value is larger than the max size of the selected video mode, the ADV611/ADV612 uses the max size of the selected mode for VEND. ...

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... These registers let the Host or DSP read sum of squares statistics from the ADV611/ADV612; using these values (with the Sum of Value, MIN Value, and MAX Value) the host or DSP can then calculate the BW and RBW values. The ADV611/ADV612 indicates that the sum of squares statistics have been updated by setting (1) the STATR bit and asserting the STAT_R pin. Read the statistics at any time ...

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... ADV611/ADV612 Sum of Luma Value Register Indirect (Read Only) Register Index 0x0AA The Sum of Luma Value register lets the host or DSP read the sum of pixel values for the Luma component in block 39. The Host reads these values through the Host Interface. [15:0] Sum of Luma, SL[15:0]. 16-bit component pixel values (undefined at reset) ...

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... Bin Widths are 8.8, unsigned, 16-bit, fixed-point values. Reciprocal Bin Widths are 6.10, un- signed, 16-bit, fixed-point values. Operation of this register is controlled by the host driver or the DSP (84 total entries) (undefined at reset). [15:0] Bin Width Values, BW[15:0] [15:0] Reciprocal Bin Width Values, RBW[15:0] REV. 0 ADV611/ADV612 –17– ...

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... Mode Control Register 2. The pin operates as follows: • Output (Master) HI during Field1 lines of video and LO otherwise • Input (Slave this input indicates Field1 lines of video Encode or Decode. This output pin indicates the coding mode of the ADV611/ ADV612 and operates as follows: • LO Decode Mode (Video Interface is output) • ...

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... Host Word Enable pins. These two input pins select the words that the ADV611/ ADV612’s direct and indirect registers access through the Host Interface; BE0–BE1 access the least significant word, and BE2–BE3 access the most significant word. For a 32-bit interface only, tie these pins to ground, making all words available ...

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... Mode Control register. ADV611/ADV612 Chip Reset. Asserting this pin returns all registers to reset state. Note that the ADV611/ADV612 must be reset at least once after power-up with this active low signal input. For more information on reset, see the SWR bit description. ...

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... In CCIR-656 mode, this control is set to Uni- polar, since the color components are offset by 128. Note that it is likely the ADV611/ADV612 will function if this control is in the wrong state, but compression performance will be degraded important to set this bit correctly. ...

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... ECL level shifters and line drivers. The functionality of HSYNC, VSYNC and FIELD Pins is dependent on three programmable modes of the ADV611/ ADV612: Master-Slave Control, Encode-Decode Control and 525-625 Control. Table X summarizes the functionality of these pins in various modes. ...

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... ADV612 video interface must use these outputs to remain in sync with the ADV611/ADV612 expected that this combination of modes would not be used frequently. Decode Mode (video data is output The ADV611/ADV612 completely manages the generation These pins are used to control the from the chip) and timing of these pins. ...

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... Compressed Data-Stream Definition Through its Host Interface the ADV611/ADV612 outputs (dur- ing encode) and receives (during decode) compressed digital video data. This stream of data passing between the ADV611/ ADV612 and the host is hierarchically structured and broken up into blocks of data as shown in Figure 13. Table V shows ...

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... Block Sequence: #SOB1, #SOB2, #SOB3, #SOB4 or #SOB5 <BW> <Huff_Data> REV. 0 “Frame N; Field 1” “Frame N; Field 2” “Frame N+1; Field 1” “Frame N+1; Field 2” “Frame N+M; Field 1” “Frame N+M; Field 2” “Required in decode to let the ADV611/ADV612 know the sequence of fields is complete.” –25– ADV611/ADV612 ...

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... A pseudo code bitstream example for one complete field of video is shown in Table XIII. A pseudo code bitstream example for one sequence of fields is shown in Table XIV. An example listing of a field of video in ADV611/ADV612 bitstream format appears in Table XVII. Y COMPONENT 6 ...

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... Mallat block 30 data—Typical BW = 0x00E4 Mallat block 21 data—Typical BW = 0x0301 Mallat block 27 data—Typical BW = 0x0281 Mallat block 24 data—Typical BW = 0x0281 Mallat block 3 data—Typical BW = 0x23D5 For Mallat Block Number /* Mallat block 6 data */ /* Mallat block 6 data */ /* Required in decode to end field sequence*/ –27– ADV611/ADV612 ...

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... The host sends the #EOS (End of Sequence) to the ADV611/ADV612 during decode after the last field in a sequence to indicate that the field sequence is complete. The ADV611/ ADV612 does not append this code to the end of encoded field sequences; it must be added by the host. ...

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... NOTE 1 This table shows ADV611/ADV612 compressed data for one field in a color ramp video sequence. The SOF# and SOB# codes in the data are in bold text. Bit Error Tolerance Bit error tolerance is ensured because a bit error within a Huffman coded stream does not cause #delimiter symbols to be misread by the ADV611/ADV612 in decode mode ...

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... THROUGH 0X4000,0013 2 DECODE IS HOST-SPECIFIC Using the ADV611/ADV612 in Computer Applications Many key features of the ADV611/ADV612 were driven by the demanding cost and performance requirements of computer applications. The following ADV611/ADV612 features provide key advantages in computer applications, such as the one in Figure 15. • Host Interface The 512 double word FIFO provides necessary buffering of compressed digital video to deal with PCI bus latency ...

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... The following circuits are recommendations only. Analog Devices has not actually built or tested these circuits. Using the Philips SAA7111 Video Decoder The SAA7111 example circuit, which appears in Figure 17, is used in this configuration on the ADV611 CCTVPIPE demon- stration board. XTAL XTAL LLC ...

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... Evaluation Board There is a low cost stand-alone evaluation board for the ADV611 called the CCTVPIPE (see block diagram). The CCTVPIPE provides a fast, simple, and low cost means of evaluating the performance of the ADV611/ADV612 and it is very similar to the evaluation board for the ADV601LC, the VideoPipe ...

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... Permanent damage may occur to devices subjected to high energy electrostatic discharges. Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. The ADV611/ADV612 latchup immunity has been demonstrated at 200 mA/–200 mA on all pins when tested to industry standard/JEDEC methods. REV. 0 Min 4 ...

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... OL Figure 22. Test Condition Voltage Reference and Device Loading TIMING PARAMETERS This section contains signal timing information for the ADV611/ADV612. Timing descriptions for the following items appear in this section: • Clock signal timing • Video data transfer timing (CCIR-656, and Multiplexed Philips formats) • ...

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... Figure 25. CCIR-656 Video—Encode Pixel (YCrCb) Transfer Timing REV VCLK CYC t VCLKO D0 t VCLKO D1 Figure 23. Video Clock Timing VALID t VDATA DC D VALID t CTRL DC D VALID t VDATA EC S ASSERTED t CTRL EC D –35– ADV611/ADV612 Min Max N N/A N N/A VALID VALID Min Max 2 N/A 5 N/A N ...

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... ADV611/ADV612 Figure 26. CCIR-656 Video—Line (Horizontal) and Frame (Vertical) Transfer Timing Note that for CCIR-656 Video—Decode and Master Line (Horizontal) timing, VDATA is synchronous with VCLKO. –36– REV. 0 ...

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... VDATA (I) CTRL Figure 28. Multiplexed Philips Video—Decode and Slave Pixel (YCrCb) Transfer Timing REV. 0 VALID t VDATA DMM D VALID t CTRL DMM D VALID t VDATA DSM OH t VDATA DSM D VALID t CTRL DSM S –37– ADV611/ADV612 Min Max N N/A N N/A VALID VALID Min Max N N/A 16 ...

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... ADV611/ADV612 Figure 29. Multiplexed Philips Video–Line (Horizontal) and Frame (Vertical) Transfer Timing –38– REV. 0 ...

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... CTRL Signals, Encode Slave Multiplexed Philips Mode, Hold CTRL_ESM_H (I) VCLK (I) VDATA (I) CTRL Figure 31. Multiplexed Philips Video—Encode and Slave Pixel (YCrCb) Transfer Timing REV. 0 VALID t VDATA EMM S ASSERTED t CTRL EMM D VALID t VDATA ESM S ASSERTED t CTRL ESM S –39– ADV611/ADV612 Min Max 2 N/A 5 N/A N N/A VALID t VDATA EMM H Min Max 2 N/A 5 N/A ...

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... Host Interface (Indirect Address, Indirect Register Data and Interrupt Mask/Status) Register Timing The diagrams in this section show transfer timing for host read and write accesses to all of the ADV611/ADV612’s direct registers, except the Compressed Data register. Accesses to the Indirect Address, Indirect Register Data, and Interrupt Mask/Status registers are slower than access timing for the Compressed Data register ...

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... VCLK periods. ACK_D_WRD WRC PWA WR D PWD VALID t t ADR D WRS ADR D WRH VALID t t DATA D WRH DATA D WRS t ACK D WRD t ACK D WROH –41– ADV611/ADV612 Min Max Unit 1 N/A N N N/A ns –10 N/A ...

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... Host Interface (Compressed Data) Register Timing The diagrams in this section show transfer timing for host read and write transfers to the ADV611/ADV612’s Compressed Data register. Accesses to the Compressed Data register are faster than access timing for the Indirect Address, Indirect Register Data, and Interrupt Mask/Status registers ...

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... ACK CD WRD Figure 35. Host (Compressed Data) Write Transfer Timing REV WRC PWD WR CD PWA VALID t ADR CD WRH VALID t t DATA CD WRS DATA CD WRH t ACK CD WROH –43– ADV611/ADV612 Min Max Unit N/A ns ...

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... DADR5 O 34 DADR4 O 35 DADR3 O 36 DADR2 O 37 DADR1 O 38 DADR0 O 39 GND GROUND RAS 40 O *Apply pull-down resistor to this pin. ADV611/ADV612 LQFP PINOUTS Pin Pin Pin Name Type CAS VDD POWER 44 VDD POWER 45 DDAT15 I/O 46 DDAT14 I/O 47 DDAT13 ...

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... GND HIRQ 22 23 LCODE FIFO SRQ 24 25 STATS R 26 VDD GND 27 28 GND 29 VDD 30 DADR8 *APPLY A 10k REV. 0 ADV611/ADV612 PIN CONFIGURATION ADV611/ADV612 LQFP TOP VIEW (Not to Scale) PULL DOWN RESISTOR TO THIS PIN –45– ADV611/ADV612 90 GND 89 NC* 88 NC* 87 VDATA0 86 VDATA1 85 VDATA2 84 ...

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... ADV611/ADV612 0.030 (0.75) 0.024 (0.60) 0.020 (0.50) COPLANARITY 0.003 (0.08) Part Number Ambient Temperature Range ADV611JST + ADV612BST – +85 C NOTES Commercial temperature range ( +70 C Plastic Thin Quad Flatpack Standard Industrial Temperature Range (– +85 C). OUTLINE DIMENSIONS Dimensions shown in inches and (mm) ...