lm4543 National Semiconductor Corporation, lm4543 Datasheet - Page 14

• Manufacturer Part Number: lm4543
• Description: Ac ?97 Codec With National 3d Sound
• Manufacturer: National Semiconductor Corporation

www.national.com
Application Information
SD_IN Slot 1: Status Address
The slot echoes the control register which a read was re-
quested on. The address echoed was initiated by a read re-
quest in the previous SD_OUT frame, slot 1.
SD_IN Slot 2: Status Data
The slot returns the control register data. The data returned
was initiated by a read request in the previous SD_OUT
frame, slot 1.
SD_IN Slot 3: PCM Record Left Channel
This slot contains the left ADC sample data. The signal digi-
tized is selected via register 1Ah and subsequently routed
through the Input Mux for recording by the left ADC.
18:12
Bits
11:0
Bits
19:4
Bits
19:2
3:0
Bit
15
14
13
12
11
19
FIGURE 7. Start of Audio Input Frame
Register Index
Register Read
Codec Ready
PCM Record
Left Channel
Description
Description
Description
Description
Slot 1 data
Slot 2 data
Slot 3 data
Slot 4 data
Reserved
Reserved
Reserved
Control
Control
Data
valid
valid
valid
valid
data
Bit
Right Audio PCM Data is
Echo of Control Register
18 bit audio sample from
Left Audio PCM Data is
0=Not Ready, 1=Ready
Status Address is valid
for which data is being
Status Data is valid
Stuffed with 0 ’s
Stuffed with 0 ’s
Stuffed with 0
Comment
Comment
Comment
Comment
returned.
left ADC
(Continued)
valid
valid
DS100907-7
14
SD_IN Slot 4: PCM Record Right Channel
This slot contains the right ADC sample data. The signal digi-
tized is selected via register 1Ah and subsequently routed
through the Input Mux for recording by the right ADC.
SD_IN Slots 5-12: Reserved
These SD_IN slots are set to 0 as they are reserved for fu-
ture use.
AC Link Low Power Mode
Reset Register (00h)
Writing any value to this register causes a register reset
which changes all of the registers back to their default val-
ues. If this register is read, the codec will return a value of
0D50h indicating that National 3D Sound is implemented
and 18 bit data is supported by both the ADCs and DACs.
Master Volume Registers (02h, 06h)
These registers allows the output levels from LINE_OUT port
and MONO_OUT port to be attenuated or muted. Each step
is nominally 1.5dB and each output can be individually
muted by setting the most significant bit to 1.
PC Beep Register (0Ah)
This register controls the level of the PC_BEEP input. The
PC_BEEP can be both attenuated and muted via register
0Ah. Step size is nominally 3dB. The signal present after the
attenuation and mute block is summed into both the left and
right channels.
Default: 8000h
Default: 8000h
Mute
Mute
Bits
Bits
19:2
1:0
1:0
0
0
0
1
0
0
1
FIGURE 8. AC Link Powerdown Timing
Right Channel
PCM Record
Description
Description
XX XXXX
Reserved
Reserved
Mx5:Mx0
1X XXXX
00 0000
01 1111
PV3:0
XXXX
0000
1111
data
18 bit audio sample from
46.5dB attenuation
46.5dB attenuation
Stuffed with 0 ’s
Stuffed with 0 ’s
45dB attenuation
0dB attenuation
0dB attenuation
Comment
Comment
right ADC
Function
Function
mute
mute
DS100907-9