lm4549b National Semiconductor Corporation, lm4549b Datasheet - Page 19

• Manufacturer Part Number: lm4549b
• Description: Ac ?97 Rev 2.1 Multi-channel Audio Codec With Sample Rate Conversion And National 3d Sound
• Manufacturer: National Semiconductor Corporation

AC Link Serial Interface Protocol
AC LINK INPUT FRAME:
SDATA_IN, CONTROLLER INPUT FROM LM4549B OUTPUT
The AC Link Input Frame contains status and PCM data from
the LM4549B control registers and stereo ADC. Input
Frames are carried on the SDATA_IN signal which is an
input to the AC ’97 Digital Audio Controller and an output
from the LM4549B codec. As shown in Figure 3, Input
Frames are constructed from thirteen time slots: one Tag
Slot followed by twelve Data Slots. The Tag Slot, Slot 0,
contains 16 bits of which 5 are used by the LM4549B. One is
used to indicate that the AC Link interface is fully operational
and the other 4 to indicate the validity of the data in the four
of the twelve following Data Slots that are used by the
LM4549B. Each Frame consists of 256 bits with each of the
twelve data slots containing 20 bits.
A new Input Frame is signaled with a low-to-high transition of
SYNC. SYNC should be clocked from the controller on a
rising edge of BIT_CLK and, as shown in Figure 6 and
Figure 7, the first tag bit in the Frame (“Codec Ready”) is
clocked from the LM4549B by the next rising edge of
BIT_CLK. The LM4549B always clocks data to SDATA_IN
on a rising edge of BIT_CLK and the controller is expected to
sample SDATA_IN on the next falling edge. The LM4549B
samples SYNC on the falling edge of BIT_CLK.
Input and Output Frames are aligned to the same SYNC
transition.
The LM4549B checks each Frame to ensure 256 bits are
received. If a new Frame is detected (a low-to-high transition
on SYNC) before 256 bits are received from an old Frame
then the new Frame is ignored i.e. no valid data is sent on
SDATA_IN until a valid new Frame is detected.
(Continued)
Bits
19:0
PCM DAC Data
Description
(Left /Right
Channels)
SLOTS 3 & 4, OUTPUT FRAME
Slots used to stream data to
DACs for all Primary or
Secondary modes.
Set unused bits to "0"
Comment
FIGURE 6. AC Link Input Frame
19
SDATA_OUT: Slots 5 to 12 – Reserved
These slots are not used by the LM4549B and should all be
stuffed with zeros by the AC ’97 Controller.
The LM4549B transmits data MSB first, in a MSB justified
format. All reserved bits and slots are stuffed with "0"s by the
LM4549B.
SDATA_IN: Slot 0 – Codec/Slot Status Bits
The first bit (bit 15, “Codec Ready”) of slot 0 in the AC Link
Input Frame indicates when the codec’s AC Link digital
interface and its status/control registers are fully operational.
The digital controller is then able to read the LSBs from the
Powerdown Control/Stat register (26h) to determine the sta-
tus of the four main analog subsections. It is important to
FIGURE 7. Start of AC Link Input Frame
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