km68257e Samsung Semiconductor, Inc., km68257e Datasheet
km68257e
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km68257e Summary of contents
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... KM68257E, KM68257EI Document Title 32Kx8 Bit High-Speed CMOS Static RAM(5V Operating) Operated at Commercial and Industrial Temperature Ranges. Revision History Rev .No. History Rev. 0.0 Initial Draft The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device ...
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... The KM68257E is a 262,144-bit high-speed Static Random Access Memory organized as 32,768 words by 8 bits. The KM68257E uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG s advanced CMOS process and designed for high-speed circuit technology ...
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... KM68257E, KM68257EI ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative Voltage on V Supply Relative Power Dissipation Storage Temperature Operating Temperature Commercial Industrial * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... KM68257E, KM68257EI AC CHARACTERISTICS ( TEST CONDITIONS Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads NOTE : The above test conditions are also applied at industrial temperature range. Output Loads(A) +5V 480 D OUT 255 ...
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... KM68257E, KM68257EI WRITE CYCLE Parameter Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time ...
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... KM68257E, KM68257EI NOTES(READ CYCLE high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address and t are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V ...
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... KM68257E, KM68257EI TIMING WAVEFORM OF WRITE CYCLE(3) Address CS WE High-Z Data in High-Z Data out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; ...
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... KM68257E, KM68257EI PACKAGE DIMENSIONS 28-SOJ-300 #28 8.51 0.12 0.335 0.005 #1 +0.10 0.43 0.95 -0. +0.004 0.0375 0.017 -0.002 28-TSOP1-0813.4F +0.10 0.20 -0.05 +0.004 0.008 -0.002 #1 0.55 #14 0.0217 0.25 TYP 0.010 0~8 0.45 ~0.75 0.018 ~0.030 #15 #14 18.82 MAX 0.741 18.41 0.12 0.725 0.005 1.30 ( 0.051 1.30 ( 0.051 +0.10 0.71 -0.05 1.27 +0.004 0.028 0.050 -0.002 13.40 0.20 0.528 0.008 #28 #15 11.80 0.10 +0.10 0.465 0.15 0.004 -0.05 +0.004 0.006 -0.002 0. 0.020 ...