dp83902a National Semiconductor Corporation, dp83902a Datasheet - Page 64

• Manufacturer Part Number: dp83902a
• Description: St-nictm Serial Network Interface Controller For Twisted Pair
• Manufacturer: National Semiconductor Corporation

15 0 Switching Characteristics
Note 1 The first port request is issued in response to the remote write command It is subsequently issued on T1 clock cycles following completion of remote DMA
cycles
Note 2 The start of the remote DMA write following WACK is dependent on where WACK is issued relative to BSCK and whether a local DMA is pending
Note 3 Assuming wackw
Note 4 WACK must be high for a minimum of 7 BSCK
Note 5 This is not a measured value but guaranteed by design
Note 1 The RESET pulse requires that BSCK and TXC be stable On power up RESET should not be raised until BSCK and TXC have become stable Several
registers are affected by RESET Consult the register descriptions for details
Note 2 The slower of BSCK or TXC clocks will determine the minimum time for the RESET signal to be low
If BSCK
If TXC
Symbol
rstw
Symbol
bprqh
wprql
wackw
bprdl
bprdh
wprq
k
k
BSCK then RESET
TXC then RESET
k
1 BSCK and no local DMA interleave no CS immediate BACK and WACK goes high before T4
Reset Pulse Width (Note 1)
e
e
8
8
Bus Clock to Port Request High (Note 1)
WACK to Port Request Low
WACK Pulse Width
Bus Clock to Port Read Low (Note 2)
Bus Clock to Port Read High
Remote Write Port Request to Port
Request Time (Notes 3 4 5)
c
c
BSCK
TXC
Parameter
Parameter
Remote DMA (Write Cycle) Recovery Time
AC Specs DP83902A Note All Timing is Preliminary (Continued)
Reset Timing
64
Min
8
Max
Min
25
12
(Note 2)
BSCK Cycles or TXC Cycles
Max
42
50
55
40
Units
TL F 11157 – 64
TL F 11157 – 45
BSCK
Units
ns
ns
ns
ns
ns