at75c140 ATMEL Corporation, at75c140 Datasheet - Page 11

• Manufacturer Part Number: at75c140
• Description: Smart Internet Appliance Processor Siap-tm
• Manufacturer: ATMEL Corporation

AIC: Advanced Interrupt
Controller
PIO: Parallel I/O
Controller
USART: Universal
Synchronous/
Asynchronous Receiver/
Transmitter
2659A–INTAP–09/02
Various features specific to static memories or SDRAM memories are listed below.
The AT75C140 has an 8-level priority interrupt controller. The interrupt controller out-
puts are connected to the fast interrupt request (NFIQ) and the normal interrupt request
(NIRQ) of the ARM7TDMI core. The processor’s NFIQ can only be asserted by the
external fast interrupt request input (FIQ). The NIRQ line can be asserted by the inter-
rupts generated by the on-chip peripherals or by the external interrupt request line IRQ0.
An 8-level priority encoder allows the application to define the priority between the differ-
ent interrupt sources. Internal sources are programmed to be level sensitive or edge
sensitive. External sources can be programmed to be positive- or negative-edge trig-
gered, or low- or high-level sensitive.
The AT75C140 has up to 48 programmable I/O lines. They can all be programmed as
inputs or outputs. To optimize the use of available package pins, most of them are multi-
plexed with external signals of on-chip peripherals.
The PIO lines are controlled by two separate and identical PIO controllers called PIOA
and PIOB.
The PIO controllers enable the generation of an interrupt on input change on each PIO
line. Some I/O lines have enough drive capability to power a LED.
The AT75C140 provides two identical full-duplex, universal synchronous/asynchronous
receiver/transmitters that interface to the APB and are connected to the Peripheral Data
Controller.
The main features are:
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Static Memories
Up to four chip select lines
Byte write or byte select lines
Two different read protocols
Programmable wait state generation
Programmable data float time
Programmable baud rate generator
Parity, framing and overrun error detection
Line break generation and detection
Automatic echo, local loopback and remote loopback channel modes
Multi-drop mode: address detection and generation
Interrupt generation
Four dedicated peripheral data controller channels
6-, 7- and 8-bit character length (9 bits in multi-drop mode)
SDRAM Memories
Byte, half-word and word access supported
CAS latency of two clock cycles supported
Auto-precharge command
Programmable refresh rate
Supports two or four internal banks
From 256 up to 2048 columns supported
From 2048 up to 8192 rows supported
AT75C140
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