a80960ht60 Intel Corporation, a80960ht60 Datasheet - Page 7

• Manufacturer Part Number: a80960ht60
• Description: 80960ha/hd/ht 32-bit High-performance Superscalar Processor
• Manufacturer: Intel Corporation

1.0
2.0
Advance Information
1.
Figure 1. 80960Hx Block Diagram
Table 1.
processors.
The 80960Hx is not “drop-in” compatible in an 80960Cx-based system. Customers can design systems that accept either 80960Hx or Cx
About This Document
This document describes the parametric performance of Intel’s 80960Hx embedded superscalar
microprocessors. Detailed descriptions for functional topics — other than parametric performance
— are published in the i960
In this document, “80960Hx” and “i960 Hx processor” refer to the products described in
Throughout this document, information that is specific to each is clearly indicated.
Intel’s 80960Hx Processor
Intel’s 80960Hx processor provides new performance levels while maintaining backward
compatibility (pin
of i960 32-bit, RISC-style, embedded processors allows customers to create scalable designs that
meet multiple price and performance points. This is accomplished by providing processors that can
run at the bus speed or faster using Intel’s clock multiplying technology
is capable of issuing 150 million instructions per second, using a sophisticated instruction scheduler
that allows the processor to sustain a throughput of two instructions every core clock, with a peak
performance of three instructions per clock. The 80960Hx-series comprises three processors, which
differ in the ratio of core clock speed to external bus speed.
80960Hx Product Description
*Processor inputs are 5 V tolerant.
Interrupt
Port
80960HA
80960HD
80960HT
Product
Interrupt Controller
Multiply/Divide Unit
Datasheet
Programmable
Execution Unit
JTAG Port
Timers
1
and software) with the i960 CA/CF processor. This newest member of the family
Core
®
1x
2x
3x
Hx Microprocessor User’s Guide (272484).
Register-Side
Machine Bus
16 Kbyte, Four-Way Set-Associative
64-bit SRC1 Bus
64-bit SRC2 Bus
64-bit DST Bus
Parallel Instruction Scheduler
Instruction Prefetch Queue
Six-Port Register File
128-Bit Cache Bus
Instruction Cache
Voltage
3.3 V
3.3 V
3.3 V
128-bit Store Bus
128-bit Load Bus
32-bit Base Bus
Memory-Side
Machine Bus
*
*
*
Operating Frequency (bus/core)
Memory Region Configuration
8 Kbyte, Four-Way Set-Associative
Register Cache - 5 to 15 sets
16/32, 25/50, 33/66, 40/80
Bus Request Queues
Address Generation Unit
Guarded Memory Unit
(Table
25/25, 33/33, 40/40
Data RAM - 2 Kbyte
Bus Controller
Data Cache
20/60, 25/75
1).The 80960Hx core
80960HA/HD/HT
Table
Control
Address
Data
1.
1