mpc5534mzq66 Freescale Semiconductor, Inc, mpc5534mzq66 Datasheet - Page 39

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mpc5534mzq66

Manufacturer Part Number
mpc5534mzq66
Description
Mpc5534 High Performance Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1
2
3
4
5
6
Freescale Semiconductor
Num
DSPI timing specified at VDD = 1.35V to 1.65V, VDDEH = 3.0V to 5.5V, VDD33 and VDDSYN = 3.0V to 3.6V, T
and CL = 50pF with SRC = 0b11.
The minimum SCK Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated
based on two MPC55xx devices communicating over a DSPI link.
The actual minimum SCK Cycle Time is limited by pad performance.
The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]
The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC]
This number is calculated assuming the SMPL_PT bit field in DSPI_MCR is set to 0b10.
11
12
Data Valid (after SCK edge)
Data Hold Time for Outputs
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA=0)
Master (MTFE = 1, CPHA=1)
Master (MTFE = 0)
Slave
Master (MTFE = 1, CPHA = 0)
Master (MTFE = 1, CPHA = 1)
Characteristic
SCK Output
(CPOL=1)
SCK Output
(CPOL=0)
SOUT
SIN
Figure 18. DSPI Classic SPI Timing — Master, CPHA = 0
PCSx
Preliminary—Subject to Change Without Notice
MPC5534 Microcontroller Data Sheet, Rev. 0
Table 26. DSPI Timing
First Data
9
First Data
2
Symbol
t
SUO
t
HO
10
4
4
Min
5.5
12
–5
–5
8
40 MHz
Data
Data
1
Max
25
18
(continued)
5
5
Last Data
Last Data
11
1
Min
5.5
–5
–5
4
66 MHz
3
Max
25
14
5
5
Min
Electrical Characteristics
5.5
–5
–5
3
80 MHz
Max
25
13
5
5
A
= TL to TH,
Unit
ns
ns
ns
ns
ns
ns
ns
ns
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