mpc5566 Freescale Semiconductor, Inc, mpc5566 Datasheet - Page 56

• Manufacturer Part Number: mpc5566
• Description: Mpc5566 High Performance Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

Revision History for the MPC5566 Data Sheet
The following table lists the information that changed in the figures or tables between Rev. 0.0 and 1.0.
56
Location
Section 3.7.1, “Input Value of Pins During POR Dependent on
Section 3.7.1, “Input Value of Pins During POR Dependent on
Section 3.7.3, “Power-Down Sequence (VRC33
Location
Figure
1, MPC5500 Family Part Numbers:
From:
Added the following text directly before this section and after
Power-on Sequence:
• Removed the 2 in the tape and reel designator in both the graphic and in the Tape and Reel Status text.
• Changed Qualification Status by adding ‘, general market flow’ to the M designator, and added an ‘S’ designator
To:
‘When powering the device, V
with the description of ‘Fully spec. qualified, automotive flow.
‘To avoid accidentally selecting the bypass clock because PLLCFG[0:1] and RSTCFG are not treated as ones
V
internal versions of PLLCFG[0:1] and RSTCFG are not powered and therefore cannot read the default state
when POR negates. V
the V
requirements when powering down.’
‘The values in
power up.
Before exiting the internal POR state, the voltage on the pins goes to high-impedance until POR negates. When
the internal POR negates, the functional state of the signal during reset applies and the weak pull devices (up or
down) are enabled as defined in the device Reference Manual. If V
signals, the weak-pull devices can pull the signals to V
To avoid this condition, minimize the ramp time of the V
enable the external circuitry connected to the device outputs.’
(1s) when POR negates, V
device by more than the V
RESET power pin (V
V
applies during power up. V
DD33
DDEH6
Table 32. Global and Text Changes Between Rev. 0.0 and 1.0 (continued)
DD33
lag specification listed in
supplies, but cannot lag both by more than the V
Table 33. Table and Figure Changes Between Rev. 0.0 and Rev. 1.0
lag specification. This V
Table 7
DDEH6
DD33
and
MPC5566 Microcontroller Data Sheet, Rev. 2.0
DD33
Table 8
DD33
DD33
) by more than the V
can lag V
DD33
lag specification in
Table
has no lead or lag requirements when powering down.’
must not lag V
Grounded)” Deleted the underscore in ORed_POR to become ORed POR.
DD33
do not include the effect of the weak pull devices on the output pins during
must not lag V
DDSYN
6. This avoids accidentally selecting the bypass clock mode because the
lag specification only applies during power up. V
Description of Changes
Description of Changes
or the RESET power pin (V
DDSYN
VDD33,” changed:
VDD33:”
DD33
DDSYN
Table
lag specification. V
and the RESET pin power (V
DDE
DD
DD33
and the RESET power pin (V
6. V
Table 8
supply to a time period less than the time required to
and V
DD33
lag specification. This V
DDEH
Pin Status for Medium / Slow Pads During the
individually can lag either V
DD
is too low to correctly propagate the logic
DDEH6
.
DD33
), but cannot lag both by more than
can lag one of the V
DDEH6
DD33
DDEH6
Freescale Semiconductor
DD33
) when powering the
lag specification only
) by more than the
has no lead or lag
DDSYN
DDSYN
or the
or