mpc5604e Freescale Semiconductor, Inc, mpc5604e Datasheet - Page 63

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mpc5604e

Manufacturer Part Number
mpc5604e
Description
Mpc5604e Microcontroller Data Sheet
Manufacturer
Freescale Semiconductor, Inc
Datasheet
3.18.11 I
Freescale Semiconductor
1
1
2
3
No.
No.
2
3
4
5
6
7
8
9
1
1
2
4
6
7
8
9
Inter Peripheral Clock is the clock at which the I
(Sys_clk).
Programming IBFD (I
listed. The I
The actual position is affected by the prescale and division values programmed in IFDR.
Inter Peripheral Clock is the clock at which the I
Because SCL and SDA are open-drain-type outputs, which the processor can only actively drive low, the time SCL
or SDA takes to reach a high level depends on external signal capacitance and pull-up resistor values.
1
1
3
1
1
1
1
1
1
Symbol
Symbol
2
C Timing
2
C interface is designed to scale the data transition time, moving it to the middle of the SCL low period.
D Start condition hold time
D Clock low time
D Data hold time
D Clock high time
D Data setup time
D Start condition setup time (for repeated start condition only)
D Stop condition setup time
D Start condition hold time
D Clock low time
D SCL/SDA rise time
D Data hold time
D SCL/SDA fall time
D Clock high time
D Data setup time
D Start condition setup time (for repeated start condition only)
D Stop condition setup time
2
C bus Frequency Divider) with the maximum frequency results in the minimum output timings
Table 35. I
Table 39. I
Preliminary—Subject to Change Without Notice
MPC5604E Microcontroller Data Sheet, Rev. 2
2
2
C SCL and SDA output timing specifications
C SCL and SDA input timing specifications
Parameter
Parameter
2
C peripheral is working in the device. It is equal to the system clock
2
C peripheral is working in the device.
Min Max
Min Max
0.0
0.0
10
10
20
10
2
8
4
2
2
6
7
2
Value
Value
99.6
99.5
Electrical characteristics
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
IP bus cycle
Unit
Unit
ns
ns
ns
ns
1
1
1
1
1
2
1
1
1
1
1
1
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