mc68194 ON Semiconductor, mc68194 Datasheet - Page 13

• Manufacturer Part Number: mc68194
• Description: Carrier Band Modem Cbm
• Manufacturer: ON Semiconductor

5.1 OVERVIEW
function providing RX clock, a 2 times (2X) RX clock, and
a 4 times (4X) RX clock for data recovery and to send
receive symbols to the MAC. Figure 5−1 is a simplified
functional schematic of the clock recovery logic. The clock
recovery is fed by the output stage of the receive amplifier.
The phase−coherent signal contains frequency components
equal to 1X and 2X the serial data rate. Figure 5−2 shows an
example of timing for a 5 Mb/s serial data rate. The RXOUT
signal drives a one−shot with a time period of 75% of 1/2 bit
time; this locks out edges caused by the higher frequency
component. The one−shot is non−retriggerable and is
triggered on both positive and negative going edges. This
produces a pulse for every edge of the lower frequency.
50% duty cycle signal equal in frequency to the lower
frequency of the phase−coherent signal. In turn, the B2
flip−flop output runs through a multiplexer to a
phase−locked loop (PLL) system. The multiplexer selects
the RXOUT signal when carrier detect is present; otherwise
the local oscillator divided by 4 is selected.
active loop filter, a voltage−controlled multivibrator
(VCM), and a divide−by−4 feedback counter. When in phase
lock, the output of the divide−by−4 feedback counter is
locked to the reference clock. In turn, the VCM 4 times clock
is also aligned with the reference clock as shown in Figure
5−2.
the 1 times clock are all in phase (when the PLL is
phase−locked) with the reference clock, and are used to do
data recovery. Note that the reference clock can be 180° out
of phase with the bit time boundaries (Figure 5−2). This does
not affect the 2X and 4X clocks which are used to sample the
data. However, RXCLK can be out of sync with the bit time
boundaries and special circuitry in the data recovery logic
detects and corrects this condition.
amplifier (carrier detect is not asserted), the multiplexer
selects the local clock as a reference. This has the advantages
of:
1. Supply a RXCLK when no data is present.
2. Holding the PLL in frequency lock so that only
3. Providing a smooth transition for RXCLK when moving
at the beginning of any transmission. The PAD−IDLE for
phase−coherent FSK is an alternating one and zero pattern,
and the PLL is capable of being locked−in well within the 24
The clock recovery circuitry is a key part of the receive
The output of the one−shot is divided by 2 to produce a
The PLL system consists of a digital phase detector, an
The 4 times clock from the VCM, the 2 times clock, and
When no valid input signal is available from the receive
The IEEE 802.4 provides a PAD−IDLE or training signal
phase−lock must be achieved when switching to the RX
signal.
from the local oscillator (at the beginning of a frame) and
vice versa (at the end of a frame). The PLL acts as an
integrator.
SECTION 5 − CLOCK RECOVERY
http://onsemi.com
13
bit times (3 octets). The design goal is to be locked−in within
12−16 bit times. Data recovered during this lockup time at
the
beginning of a transmission can be invalid because the PLL
clocks are not sync’ed. As a result the data recovery logic
forces silence for 17−18 bit times after the carrier detect
switches the reference clock (via the multiplexer) at the
beginning of a received transmission.
5.2 ONE−SHOT
transitions due to the higher frequency component of the
phase−coherent signal. The one−shot is non−retriggerable
and fires off both edges of the incoming RXOUT signal. The
time period should be set to 75% of half the bit time. As an
example, the 5 Mb/s data rate has a 200 nsec bit time and the
one−shot period then has a period of 75 nsec.
Figure 5−1. Clock Recovery Logic
(4X BIT RATE)
As previously stated, the one−shot is used to lock out the
75% OF 1/2
BIT TIME
ONE−SHOT
RPW
R
RXOUT
REF CLK
(IN LOCK)
EXT
(B2)*
RXOUT
RECOVERY
Figure 5−2. Clock Recovery Timing Signals
SHOT
OSC B 4
ONE
VCM
*NOTE: Ref clock can also be 180° out of phase with bit time.
LOCAL
+ 5 V
SELECT
DATA
CPW
C
EXT
BIT TIME
1/2
B2
1"
MUX
SET
PW
−
0"
PD
D*
1"
B4
U*
0"
C1
OP
AMP
Q
ND1"
VCM
VCM
ACTIVE FILTER
ND PAIR
2X CLOCK
4X CLOCK
CBM
C
VCM
C2
ND2"
VCX