mc68181 Freescale Semiconductor, Inc, mc68181 Datasheet - Page 73

• Manufacturer Part Number: mc68181
• Description: Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

All Frame Mode Packet
MOTOROLA
Byte
3
2
1
0
The All Frame Mode Packet is used to decrement temporary address enable counters
by one, decrement the all frame mode counter by one, and/or enable or disable
forcing All Frame mode. If All Frame mode is enabled, the FLEX chip IC will attempt
to decode every frame and send a Status Packet with the EOF (End-Of-Frame) bit set
at the end of every frame. All Frame mode is enabled if any temporary address enable
counter is non-zero, or, the All Frame mode counter is non-zero, or, the force All
Frame Mode bit is set. Both the All Frame mode counter and the temporary address
enable counters can only be incremented internally by the FLEX chip IC and can only
be decremented by the host. The FLEX chip IC will increment a temporary address
enable counter whenever a short instruction vector is received assigning the
corresponding temporary address. The FLEX chip IC will increment the All Frame
mode counter whenever an alphanumeric, HEX / binary, or secure vector is received.
When the host determines that a message associated with a temporary address, or a
fragmented message has ended, then the appropriate temporary address counter or
All Frame mode counter should be decremented by writing an All Frame Mode
Packet to the FLEX chip IC in order to exit the All Frame mode, thereby improving
battery life. Neither the temporary address enable counters nor the All Frame mode
counter can be incremented past the value 127 or decremented past the value 0 (i.e., it
will not roll over). The temporary address enable counters and the All Frame mode
counter are initialized to 0 at reset and when the decoder is turned off. The ID of the
All Frame Mode Packet is 3.
•
•
•
•
DTA
DTA
Bit 7
DAF
The minimum time between steps 1 and 2 is 2 ms or the programmed shut
down time, whichever is greater. The programmed shut down time is the sum
of all the of the times programmed in the used Receiver Shut Down Settings
Packets.
There is no maximum time between steps 1 and 2.
The minimum time between steps 2 and 3 is 2 ms.
The maximum time between steps 2 and 3 is the programmed warm up time
minus 2 ms. The programmed warm up time is the sum of all the of the times
programmed in the used Receiver Warm Up Settings Packets.
0
15
7
Freescale Semiconductor, Inc.
Table B-9 All Frame Mode Packet Bit Assignments
For More Information On This Product,
DTA
DTA
Bit 6
FAF
MC68181 Technical Data Sheet
0
14
6
Go to: www.freescale.com
DTA
DTA
Bit 5
0
0
13
5
DTA
DTA
Bit 4
0
0
12
4
DTA
DTA
Bit 3
0
0
Host-to-Decoder Packet Descriptions
11
3
DTA
DTA
Bit 2
0
0
10
2
DTA
DTA
Bit 1
1
0
9
1
DTA
DTA
Bit 0
MC68181
1
0
B-13
8
0