mc68160a Freescale Semiconductor, Inc, mc68160a Datasheet
mc68160a
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mc68160a Summary of contents
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... Freescale Semiconductor, Inc. Enhanced Ethernet Transceiver The MC68160A Enhanced Ethernet Interface Circuit is a BiCMOS device which supports both IEEE 802.3 Access Unit Interface (AUI) and 10BASE–T Twisted Pair (TP) Interface media connections through external isolation transformers. It encodes NRZ data to Manchester data and supplies the signals which are required for data communication via 10BASE– ...
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... TCLK 2 CS0 Jabber CS1 Control CS2 TPEN Mode APORT Select TPAPCE TPSQEL TPFULDL LOOP TPJABB TPTX+ For More Information On This Pro MC68160A Mux Collision Detect Mux Collision Detector Control Driver Link Pre–emphasis Pulse Control Control Squelch Test Circuit TPTX– ...
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... For More Information On This Pro ANALOG IC DEVICE DATA MC68160A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... RCLK. In the standby mode, RENA is driven to the high impedance state. Receive Data Output: Recovered data, synchronous to RCLK. Following a reset operation, 100 ms should be allowed before attempting to read data processed by the MC68160A, B and C. This delay is needed to insure that the receive phase locked loop is properly synchronized with incoming data ...
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... LOOP as a test mode is enabled that disrupts normal operation. Twisted Pair Automatic Polarity Correction Enable: When TPAPCE is high, automatic polarity correction is enabled, and MC68160A will internally correct for a polarity fault on the receive circuit. Additionally, when TPAPCE is high, the presence of a polarity fault is indicated on TPPLR ...
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... Twisted Pair Receiver Inputs (TPRX+, TPRX–) are reversed, TPPLR will be driven to the low logic state to indicate the fault. TPPLR remains low when the MC68160A, AB and AC has automatically corrected for the reversed wires. If the twisted pair link integrity tests fail, this output will be driven to the high logic state ...
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... CS0 CS1 CS2 NOTE: In standby mode, the MC68160A consumes less power supply current than in any other mode. Additionally, in the standby mode, all of the controller inputs and outputs are driven to the high impedance state. When the standby mode is deasserted, an internal reset pulse of approximately 6.0 s duration is generated. ...
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... ESD threshold voltage is designed to 700 V Human Body Model. DC ELECTRICAL CHARACTERISTICS ambient operating temperature and power supply voltage ranges.) Characteristic POWER SUPPLY Undervoltage Shutdown Threshold Power Supply Current For More Information On This Pro MC68160A ELECTRICAL CHARACTERISTICS Symbol Min Max Unit T stg – 65 ...
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... Freescale Semiconductor, Inc. DC ELECTRICAL CHARACTERISTICS limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160A except where noted.) Characteristic TTL COMPATIBLE INPUTS TTL Compatible Input Voltage Low State High State Input Current TTL Compatible Input Pins (Note 1) Input Current TENA TTL Compatible Input Pin: with Pull– ...
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... Freescale Semiconductor, Inc. DC ELECTRICAL CHARACTERISTICS limits apply over the recommended ambient operating temperature and power supply voltage ranges for each MC68160A except where noted.) Characteristic TWISTED PAIR TRANSMITTER OUTPUTS Differential Output Voltage IDLE Mode Open Circuit Differential Output Impedance TRANSMISSION Mode ...
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... This is realized with the 39 external resistors shown in Figures 3, 4 and 5, together with the internal driver output resistance. Figure 6. AUI Common Mode Termination For More Information On This Pro ANALOG IC DEVICE DATA MC68160A Device Figure 5. Test Load B3 39 RCM + 10 k VCMD – 39 Figure 7 ...
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... Load on specified output ground, unless otherwise noted Rising Edge Figure 8. X1 Input Voltage Levels for Timing Measurements 4.0V 0V For More Information On This Pro MC68160A (Unless otherwise noted, minimum and maximum limits apply over the recommended Symbol ...
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... Figure 10. Transmit Timing (Motorola Mode 1.5V 1.5V TCLK 1.5V TENA TX Figure 11. Receive Timing (Motorola Start of Frame) 1.5V RENA t 25 1.5V RCLK For More Information On This Pro OROLA ANALOG IC DEVICE DATA MC68160A 0.8V 1.5V 1.5V 1. 1.5V 1. ...
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... Freescale Semiconductor, Inc. Figure 12. Receive Timing (Motorola End of Frame) RENA RCLK RX CONTROLLER TRANSMIT SWITCHING (Intel Mode – Support by MC68160A Only) Characteristic TXC Cycle Time TXC High and Low Time TXC Rise and Fall Time TXD Setup Time to TXC TXD Hold Time to TXC ...
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... Freescale Semiconductor, Inc. CRS RXC RXD CONTROLLER TRANSMIT SWITCHING (Fujitsu Mode – Supported by MC68160A Only) Characteristic TCKN Cycle Time TCKN High and Low Time TCKN Rise and Fall Time TXD Setup Time to TCKN TXD Hold Time to TCKN TEN Setup Time to TCKN ...
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... RCKN RXD Figure 17. Receive Timing (Fujitsu End of Frame) XCD RCKN RXD CONTROLLER TRANSMIT SWITCHING (National Mode – Supported by MC68160A Only) Characteristic TXC Cycle Time TXC High and Low Time TXC Rise and Fall Time TXD Setup Time to TXC TXD Hold Time to TXC ...
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... TXC t 111 t 115 1.5V TXE 1.5V TXD Figure 19. Receive Timing (National) 1.5V CRS t 122 t 125 1.5V 1.5V RXC t 121 RXD For More Information On This Pro ANALOG IC DEVICE DATA Go to: www.freescale.com MC68160A 3V 1.5V 0.8V 0.8V t 112 t 112 t 113 t 114 1.5V t 126 t 120 3V 0.8V 1.5V 1.5V t 123 t 123 t 124.1 t 124 1.5V 1.5V t 116 1.5V 1.5V t 127 1 ...
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... H 39 Figure 22. Test Load C 200 H 39 47.5 V out 39 47.5 NOTE: A total of 50 This is realized with the 39 together with the internal driver output resistance. For More Information On This Pro MC68160A Symbol V OCMTP t 130 t 131 t 132 t 133 t 134 t 135 t 136 t 137 t 137 t 137 t 138 ...
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... Levels) TPTX +/– Differential (Pre–Emphasis) Figure 25. TPTX Transmit Timing (End of Frame) Switching t 136 90% TPTX +/– Differential Figure 26. RENA Deassert Delay from TENA TENA RENA For More Information On This Pro OROLA ANALOG IC DEVICE DATA MC68160A 1. 133 1.5V t 134 1. ...
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... TPSQEL Disable Delay Time (See Figure 29) NOTE: The load attached to the specified output capacitor connected to ground, unless otherwise noted. TPTX –585mV (Differential) TPJABB CLSN For More Information On This Pro MC68160A Figure 27. TPTX+/– Link Pulse Timing t 142 t 141 585mV 50mV Figure 28. TPJABB Switching 585mV t 160 1 ...
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... Link beats further apart in time than this range of values are not considered consecutive, and are rejected. Figure 30. Test Load H 1.0 H 200 H 100pF 100pF 100 1.0 H For More Information On This Pro OROLA ANALOG IC DEVICE DATA MC68160A 2V t 171 t 170 Symbol V IDFSTP t 180 t 181 t 182 t 183 ...
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... TPRX+/– RENA t 181 RCLK RX Figure 33. RENA Deassertion Delay from Last Valid Positive Transition of TPRX Pair TPRX+/– RENA Figure 34. TP Receive Link Integrity Switching t 201 TPRX TPLIL For More Information On This Pro MC68160A Bit n Bit n+1 Bit n 182 t 183 1.5V 1.5V Bit n ...
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... NOTE: Load on specified output ground, unless otherwise noted. RENA 1.5V TENA t 210 1.5V CLSN TPFULDL 1.5V CLSN TPFULDL 1.5V RENA For More Information On This Pro OROLA ANALOG IC DEVICE DATA MC68160A Figure 35. TPTX Collision Timing Figure 36. TPTX Full Duplex Timing 1.5V t 220 t 221 1.5V 1.5V Figure 37. TPTX Full Duplex Timing 1.5V t 223 t 222 1.5V 1.5V Go to: www.freescale.com ...
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... The squelch circuits are disabled by the first valid negative differential pulse on either the AUI receive data or collision pair positive differential pulse occurs on either the AUI receive data or collision pair > 175 ns, end of frame is assumed and squelch circuitry is turned on. For More Information On This Pro MC68160A Symbol resistor. ...
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... If the EEST isn’t receiving data, the controller may initiate transmission. NRZ data from the communications controller SIA interface is encoded by the MC68160A into Manchester Code in preparation for transmission on the media. The data is then applied to either the AUI or TP port. If the data was transmitted using the 10BASE– ...
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... Collision is the occurrence of simultaneous transmit activity by two or more stations on the network. In the event of collision, the data transfer paths are unaffected. If the MC68160A is in the twisted pair mode, collision is detect by simultaneous receive and transmit activity the AUI mode, collision is detected by activity on the ACX+/– pins. In either case, if collision is detected, the CLSN pin will assert to notify the communications controller ...
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... TPFULDL high and TPSQEL low. Then, while keeping and the TPSQEL low, raise LOOP after 300 ms lower TPFULDL. This will put the MC68160A into test mode but also resets the MC68160A. After 500 ms lower LOOP to get out of the test uu mode. TPFULDL may then be de–asserted if desired. C5) The MC68160A is now ready for operation ...
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... TPPLR TPJABB TPEN GNDCTL TCLK TENA RCLK CLSN TX For More Information On This Pro MC68160A Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ATX+ ATX– ARX+ ARX– ACX+ ACX– ...
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... C –H– –T– 3 SEATING 4X PLANE 0.05 (0.002 VIEW AA For More Information On This Pro OROLA ANALOG IC DEVICE DATA MC68160A OUTLINE DIMENSIONS FB SUFFIX PLASTIC PACKAGE CASE 848D-03 (LQFP–52) ISSUE C 4X TIPS 0.20 (0.008) T L– –M– PLATING ...
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... Freescale Semiconductor, Inc. MC68160A NOTES For More Information On This Pro Go to: www.freescale.com ANALOG IC DEVICE DATA ...
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... Freescale Semiconductor, Inc. For More Information On This Pro OROLA ANALOG IC DEVICE DATA MC68160A NOTES Go to: www.freescale.com 31 ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Go to: www.freescale.com MC68160A/D OROLA ANALOG IC DEVICE DATA ...