mc68ec030 Freescale Semiconductor, Inc, mc68ec030 Datasheet - Page 16

• Manufacturer Part Number: mc68ec030
• Description: Second-generation 32-bit Enhanced Embedded Controller
• Manufacturer: Freescale Semiconductor, Inc

EXCEPTION PROCESSING SEQUENCE
STATUS
1 6
Exception processing occurs in four steps. During the first step, an internal copy is made of the status
register. After the copy is made, the special controller state bits in the status register are changed. The S-
bit is set, putting the controller into the supervisor state. Also, the T1 and T0 bits are negated, allowing
the exception handler to execute unhindered by tracing. For the reset and interrupt exceptions, the
interrupt priority mask is also updated.
In the second step, the vector number of the exception is determined. For interrupts, the vector number
is obtained by a controller read that is classified as an interrupt acknowledge cycle. For coprocessor-
detected exceptions, the vector number is included in the coprocessor exception primitive response.
For all other exceptions, internal logic provides the vector number. This vector number is then used to
generate the address of the exception vector.
The third step is to save the current controller status. The exception stack frame is created and filled on
the current supervisor stack. To minimize the amount of machine state that is saved, various stack frame
sizes are used to contain the controller state, depending on the type of exception and where it occurred
during instruction execution. If the exception is an interrupt and the M-bit is set, the M-bit is then cleared,
and the short four-word exception stack frame that is saved on the master stack is also saved on the
interrupt stack. If the exception is a reset, the M-bit is simply cleared, and the reset vector is accessed.
The MC68EC030 provides the same extensions to the exception stacking process as the MC68020,
MC68030, and MC68040. If the M-bit is set, the master stack pointer (MSP) is used for all task-related
exceptions. When a nontask-related exception occurs (i.e., an interrupt), the M bit is cleared, and the
interrupt stack pointer (ISP) is used. This feature allows all the task's stack area to be carried within a single
controller control block, and new tasks can be initiated by simply reloading the MSP and setting the M-bit.
The fourth and last step of exception processing is the same for all exceptions. The exception vector
offset is determined by multiplying the vector number by four. This offset is then added to the contents of
the vector base register (VBR) to determine the memory address of the exception vector. The new
program counter is fetched from the exception vector. The instruction at the address given in the
exception vector is fetched, and normal instruction decoding and execution is started.
The MC68EC030 provides the
associated with the processing of data pipelined in the pipeline. Since bus cycles are independently
controlled and scheduled by the bus controller, information concerning the processing state of the
microsequencer is not available by monitoring bus signals by themselves. The internal activity identified
by the
the microsequencer has halted, and instruction pipeline refills.
internal microsequencer activity and are not directly related to bus activity.
STATUS
and
REFILL
and
REFILL
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signals include instruction boundaries, some exception conditions, when
STATUS
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and
REFILL
signals to identify internal microsequencer activity
STATUS
and
REFILL
track only the
M O T O R O L A