mc68307ad Freescale Semiconductor, Inc, mc68307ad Datasheet - Page 23
mc68307ad
Manufacturer Part Number
mc68307ad
Description
Integrated Multiple-bus Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68307AD.pdf
(34 pages)
.
PRELIMINARY AC TIMING SPECIFICATIONS
MOTOROLA
(V
NOTES:
CC
Num
56
55
57
58
a. For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum
b. Actual value depends on clock period.
c. When AS, CSx and R/W are equally loaded ( 20%), subtract 5 ns from the values given in these columns.
d. If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK asserted to data
e. For power-up, the MC68307 must be held in the reset state for 128 clock cycles after CLK and V
= 5.0V
e
columns.
setup time (#31) requirement can be ignored. The data must only satisfy the data-in to clock low setup time
(#27) for the following clock cycle.
stable to allow stabilization of on-chip circuitry. After the system is powered up, #56 refers to the minimum
pulse width required to reset the controller.
R/W asserted to data bus impedance change
HALT/RESET pulse width
BGACK negated to AS, CSx, LDS, UDS, R/W driven
BR negated to AS, CSx, LDS, UDS, R/W driven
0.5V or 3.3Vdc
0.3V; GND = 0Vdc; T
MC68307 TECHNICAL INFORMATION
Characteristic
A
= T
L
to T
H
) (See Figures 8–10)
Min
1.5
1.5
40
10
8.33 MHz
3.3V
Max
—
—
—
—
Min
16.67 MHz
1.5
1.5
20
10
CC
5V
become
Max
—
—
—
—
Unit
Clks
Clks
Clks
ns
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