mc68hc11k4 Freescale Semiconductor, Inc, mc68hc11k4 Datasheet - Page 172
mc68hc11k4
Manufacturer Part Number
mc68hc11k4
Description
Mc68hc11k1 Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC11K4.pdf
(290 pages)
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Serial Peripheral Interface (SPI)
8.5 SPI System Errors
8.5.1 Mode Fault Error
Technical Data
172
CPOL selects an active high or low clock edge. CPHA selects one of two
transfer formats. When CPHA is cleared, the shift clock is ORed with SS.
Each slave’s SS pin must be pulled high before it writes the next output
byte to its data register. If a slave writes to its data register while SS is
low, a write collision error occurs. When CPHA is set, SS may be left low
for several SPI characters. When there is only one SPI slave MCU, its
SS line may be tied to V
The SPI configuration determines the characteristics of a transfer in
progress. For a master, a transfer begins when data is written to SPDR
and ends when SPIF is set. For a slave with CPHA cleared, a transfer
starts when SS goes low and ends when SS returns high. In this case,
SPIF is set at the middle of the eighth SCK cycle when data is
transferred from the shifter to the parallel data register, but the transfer
is still in progress until SS goes high. For a slave with CPHA set, transfer
begins when the SCK line goes to its active level, which is the edge at
the beginning of the first SCK cycle. The transfer ends when SPIF is set.
SCK in a slave must be inactive for at least two E-clock cycles between
byte transfers.
Two types of errors can be detected by the SPI system:
A mode fault error occurs when the SS input line of an SPI system
configured as a master goes to active low, usually because two devices
have attempted to act as master at the same time. The resulting
contention between push-pull CMOS pin drivers can cause them
permanent damage. The mode fault disables the drivers in an attempt to
protect them. The MSTR control bit in the SPCR and all four DDRD
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
A mode fault error can occur when multiple devices attempt to act
in master mode simultaneously.
A write collision error results from an attempt to write data to the
SPDR while a transmission is in progress.
Serial Peripheral Interface (SPI)
Go to: www.freescale.com
SS
if CPHA = 1 at all times.
M68HC11K Family
MOTOROLA
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