mc68hc05bs8 Freescale Semiconductor, Inc, mc68hc05bs8 Datasheet - Page 41

• Manufacturer Part Number: mc68hc05bs8
• Description: Mc68hc05 Family Of Low-cost Single-chip Microcontrollers.
• Manufacturer: Freescale Semiconductor, Inc

next pulse should not occur until the MCU software has exited the routine (an RTI occurs). The
second configuration shows several interrupt lines wired-OR to perform the interrupt at the
processor. Thus, if the interrupt lines remain low after servicing one interrupt, the next interrupt is
recognized.
Note:
5.2.2.2
The CPU will process an Sync Signal Processor VSYNC interrupt if the following conditions are
satisfied:
This interrupt will vector to the interrupt service routine located at the address specified by the
contents of $3FF8 and $3FF9. The VSYNC interrupt latch will be cleared automatically by fetching
of these vectors.
Refer to Section 9 for detailed description of Sync Signal Processor.
5.2.2.3
The hardware M-Bus interrupt is enabled when the M-Bus Interrupt Enable bit (MIEN) of M-Bus
Control register is set, provided the interrupt mask bit of the Condition Code register is cleared.
The interrupt service routine address is specified by the contents of memory location $3FF2 and
$3FF3.
MIF - M-Bus Interrupt
When this bit is set, an interrupt is generated to the CPU if MIEN is set. This bit is set when one
of the following events occurs:
MC68HC05BS8
M-Bus Status Register
1) the I-bit of the CCR is cleared,
2) the VSIE bit of the Interrupt Line Count register (ILCR) is set, and
3) the value of the horizontal line counter matches the value set in the ILCR.
1 (set)
0 (clear) –
1) Completion of one byte of data transfer. It is set at the falling edge of the 9th
The internal interrupt latch is cleared in the first part of the service routine; therefore,
one (and only one) external interrupt pulse could be latched during t
as soon as the I-bit is cleared.
clock - MCF set.
Sync Signal Processor Interrupt
M-Bus Interrupts
–
An M-Bus interrupt has occurred.
An M-Bus interrupt has not occurred.
Address bit 7
$001A
RESETS AND INTERRUPTS
MCF
MAAS MBB
bit 6
bit 5
bit 4
MAL
bit 3
SIF
SRW
bit 2
bit 1
MIF
ILIL
RXAK 1000 0001
bit 0
and serviced
on reset
State
TPG
5