mc68hc05p9a Freescale Semiconductor, Inc, mc68hc05p9a Datasheet - Page 113

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mc68hc05p9a

Manufacturer Part Number
mc68hc05p9a
Description
Hcmos Microcontroller Unit
Manufacturer
Freescale Semiconductor, Inc
Datasheet
15-mc68hc05p9a
MOTOROLA
MSTR — Master Mode Select
Clearing SPE during a transmission aborts the transmission, resets
the bit counter, and returns the port to its normal I/O function. Reset
clears SPE.
This read/write bit configures the SIOP for master mode. Setting
MSTR initializes the PB7/SCK pin as the serial clock output. Clearing
MSTR initializes the PB7/SCK pin as the serial clock input. MSTR can
be set at any time regardless of the state of SPE. Reset clears MSTR.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = SIOP enabled
0 = SIOP disabled
1 = Master mode selected
0 = Slave mode selected
Go to: www.freescale.com
SIOP
I/O Registers
SIOP
113

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