mc68hc908rk2 Freescale Semiconductor, Inc, mc68hc908rk2 Datasheet - Page 143

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mc68hc908rk2

Manufacturer Part Number
mc68hc908rk2
Description
Hcmos Microcontroller Unit
Manufacturer
Freescale Semiconductor, Inc
Datasheet
8.8.4 ICG DCO Divider Register
MC68HC908RK2
MOTOROLA
Rev. 4.0
Address: $0039
Reset:
Read:
Write:
DDIV3–DDIV0 — ICG DCO Divider Control Bits
These bits indicate the number of divide-by-twos (DDIV) that follow
the digitally controlled oscillator. Incrementing DDIV will add another
divide-by-two, doubling the period (halving the frequency).
Decrementing has the opposite effect. DDIV cannot be written when
ICGON is set to prevent inadvertent frequency shifting. When ICGON
is set, DDIV is controlled by the digital loop filter. The range of valid
values for DDIV is from $0 to $9. Values of $A–$F are interpreted the
same as $9. Since the DCO is active during reset, reset has no effect
on DSTG and the value may vary.
Bit 7
R
R
0
Internal Clock Generator Module (ICG)
Figure 8-14. ICG DCO Divider Register (ICGDVR)
= Reserved
R
6
0
R
5
0
R
4
0
U = Unaffected
Internal Clock Generator Module (ICG)
DDIV3
U
3
DDIV2
U
2
Advance Information
DDIV1
U
1
I/O Registers
DDIV0
Bit 0
U
143

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