at43usb355 ATMEL Corporation, at43usb355 Datasheet
at43usb355
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at43usb355 Summary of contents
Page 1
... It is supported by a standard set of peripherals such as timer/counter modules, watchdog timer and internal and external interrupt sources. The major peripheral included in the AT43USB355 is a full-speed USB 2.0 Hub with an embedded function and a 12-channel Analog-to-Digital Converter (ADC) for use in applications such as game controllers ...
Page 2
... Pin Configuration Figure 1. AT43USB355E 64-lead LQFP Figure 2. AT43USB355M 64-lead LQFP AT43USB355 2 SCK 49 SSN 50 51 MOSI 52 MISO 53 CEXT3 VCC3 54 VSS3 55 AT43USB355E-AC PD7 56 57 PD6 PD5 58 XTAL1 59 XTAL2 60 LFT 61 PD4 62 PD3 63 PD2 64 49 PF1 PF2 PF3 52 CEXT3 53 VCC3 54 VSS3 55 AT43USB355M-AC 56 PD7 PD6 ...
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... Pin# Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Input Input AT43USB355 Signal 33 ADC11 34 ADC10 35 ADC9 36 ADC8 37 ADC7 38 ADC6 39 ADC5 40 ADC4 41 ADC3 42 ADC2 43 ADC1 44 ADC0 45 ...
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... Bi-directional DP[2,3] Bi-directional DM[2,3] Bi-directional PA[0:7] Bi-directional PB[0:7] Bi-directional AT43USB355 4 Function 5V Digital Power Supply 5V Power Supply for the ADC Digital Ground Ground for the ADC External Capacitors for Power Supplies – High quality 2.2 µF capacitors must be connected to CEXT1, 2 and 3 for proper operation of the chip. External Capacitor for Analog Power Supply – A high quality 0.33 µF capacitor must be connected to CEXTA for proper operation of the chip. Oscillator Input – ...
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... MISO, SPI Slave Data Out. ICP after download complete Slave Select – In the AT43USB355E, this pin enables the external serial memory. In the AT43USB355M, this pin has no function and can be left floating or connected to VCEXT. ADC Input[0:11] – 12-bit input pins for the ADC. ...
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... Figure 3. AT43USB355 Enhanced RISC Architecture 12K x 16 Program Memory Instruction Register Instruction Decoder Control Lines AT43USB355 6 Program Status and Counter Control General-purpose Registers ALU 1024 x 8 SRAM 27 GPIO Lines USB Hub and Function Interrupt Unit 8-bit Timer/Counter 16-bit Timer/Counter Watchdog ...
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... On-chip ADC The embedded USB hardware of the AT43USB355 is a compound device, consisting port hub with a permanently attached function on one port. The hub and attached function are two independent USB devices, each having its own device addresses and control end-points. ...
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... Table 1. AVR CPU General-purpose Working Register Register File Register R13 R14 R15 R16 R17 .. R26 R27 R28 R29 R30 R31 AT43USB355 8 Address Comment $00 $01 $02 $0D $0E $0F $10 $11 $1A X-register low byte $1B X-register high byte $1C Y-register low byte $1D Y-register high byte ...
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... The AT43USB355E contains 24K bytes on-chip downloadable memory for program storage while the AT43USB355M has a masked programmable ROM. Since all instructions are 16- or 32-bit words, the program memory is organized as 12K x 16. The AT43USB355 Program Counter (PC bits wide, thus addressing the 12,288 program memory addresses. ...
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... The program memory of the AT43USB355E is automatically written with data stored in an external serial EEPROM during the chip's power-on reset sequence. The power-on reset is the only way the on-chip program memory of the AT43USB355E will be written or modified. The two versions of the AT43USB355 are binary compatible. A firmware written for the AT43USB355E will work unaltered on the AT43USB355M ...
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... Figure 5. READ Timing SRAM Data Table 3 summarizes how the AT43USB355 SRAM Memory is organized. The lower 1120 Data Memory locations address the Register file, the I/O Memory and the internal data SRAM. The Memory first 96 locations address the Register File + I/O Memory, and the next 1024 locations address the internal data SRAM ...
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... Table 2. SRAM Organization AT43USB355 12 Register File R0 R1 R30 R31 I/O Registers $00 $01 $3E $3F Data Address Space $0000 $0001 $001E $001F $0020 $0021 $005E $005F Internal SRAM $0060 $0061 $025E $045F USB Registers $1F00 $1FFE $1FFF 2603G–USB–04/06 ...
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... Function End-point 3 FIFO Data Register HBYTE_CNT0 Hub End-point 0 Byte Count Register FBYTE_CNT0 Function End-point 0 Byte Count Register FBYTE_CNT1 Function End-point 1 Byte Count Register FBYTE_CNT2 Function End-point 2 Byte Count Register FBYTE_CNT3 Function End-point 3 Byte Count Register HSTR Hub Status Register HPCON Hub Port Control Register AT43USB355 13 ...
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... AT43USB355 14 Name Function HPSTAT3 Hub Port 3 Status Register HPSTAT2 Hub Port 2 Status Register HPSTAT1 Hub Port 1 Status Register HPSCR3 Hub Port 3 Status Change Register HPSCR2 Hub Port 2 Status Change Register ...
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... TX PACKET READY STALL_SENT-ACK FORCE STALL TX PACKET READY STALL_SENT-ACK FORCE STALL TX PACKET READY STALL_SENT-ACK FORCE STALL TX PACKET READY STALL_SENT-ACK FORCE STALL TX PACKET READY STALL_SENT-ACK AT43USB355 Bit 2 Bit 1 Bit 0 RMWUPE CONFG HADD EN FRWUP RSM GLB SUSP FRWUP IE RSM IE GLB SUSP IE FRWUP MSK RSM MSK ...
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... I/O Memory The I/O space definition of the AT43USB355 is shown in the following table: Table 5. I/O Memory Space I/O (SRAM) Address $3F ($5F) $3E ($5E) $3D ($5D) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $35 ($55) $33 ($53) $32 ($52) $2F ($4F) $2E ($4E) $2D ($52) $2C ($52) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $25 ($45) $24 ($44) $21 ($41) $1B ($4B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) ...
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... AT43USB355 has 3 downstream ports. The embedded function is permanently attached to Port 1. Ports 2 and 3 are available as external ports. The actual number of ports used is strictly defined by the firmware of the AT43USB355 and can vary from Because the exact configuration is defined by firmware, ports 2 and 3 may even function as perma- nently attached ports as long as the Hub Descriptor identifies them as such ...
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... Figure 6. USB Hardware AT43USB355 18 Port 0 XCVR Hub Repeater Serial Interface Engine Port 1 Hub Function Interface Interface Unit Unit AVR Microcontroller Port 2 XCVR Port 3 XCVR Data Address Control 2603G–USB–04/06 ...
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... V the chip through the CEXT1 and CEXTA pins. I/O Pin The I/O pins of the AT43USB355 should not be directly connected to voltages less than V more than the voltage at the CEXT pins necessary to violate this rule, insert a series Characteristics resistor between the I/O pin and the source of the external signal source that limits the current into the I/O pin to less than 2 mA ...
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... Figure 7. Oscillator and PLL Reset and The AT43USB355 provides 20 different interrupt sources with 11 separate reset vectors, each with a separate program vector in the program memory space. Eleven of the interrupt sources Interrupt Handling share 2 interrupt reset vectors. These 11 are the USB related interrupts. All interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the status reg- ister in order to enable the interrupt ...
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... Some applications may include firmware routines lasting for long periods of time that cannot be interrupted. At the same time, other less critical events may need attention after the critical routine is completed. The AT43USB355 solves this problem by having interrupt mask registers in addition to the interrupt enable registers of the USB related interrupts. The difference between the mask and the enable registers is: • ...
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... USB Reset – The AT43USB355 has a feature to separate the USB and microcontroller resets. This feature is enabled by setting the BUS INT EN, bit 3 of the SPRSIE register. A USB bus reset is defined as a SE0 (single ended zero least 4 slow speed USB clock cycles received by Port0 ...
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... By holding the pin low for a period after V Power-on Reset period can be extended. 2603G–USB–04/06 USB Reset OR Cntr Reset 14-bit Cntr has reached the power-on threshold voltage, regardless of the V CC AT43USB355 ON S FSTRT R directly or via an CC has been applied, the CC ...
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... TIME-OUT INTERNAL RESET Non-USB Related The AT43USB355 has two non-USB 8-bit Interrupt Mask control registers; GIMSK (General Interrupt Mask Register) and TIMSK (Timer/Counter Interrupt Mask Register). Interrupt Handling When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled ...
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... Note that external level interrupt does not have a flag, and will only be remembered for as long as the interrupt condition is active. 2603G–USB–04/06 AT43USB355 25 ...
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... INT0 is configured as an output. The corresponding interrupt of Inter- rupt Request 0 is executed from program memory address $002. See also “External Interrupts” on page 29. • Bits 5..0 – Res: Reserved Bits These bits are reserved bits in the AT43USB355 and always read as zero. General Interrupt Flag Register – GIFR Bit $3A ($5A) ...
Page 27
... Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $007) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the TIFR. • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the AT43USB355 and always reads zero. 2603G–USB–04/06 7 ...
Page 28
... When the SREG I- bit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed. • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the AT43USB355 and always reads zero. AT43USB355 28 7 ...
Page 29
... During these 4 clock cycles, the Program Counter (2 bytes) is popped back from the Stack, the Stack Pointer is incremented by 2, and the I flag in SREG is set. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruc- tion before any pending interrupt is served. 2603G–USB–04/06 AT43USB355 29 ...
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... This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode. When SM is set (1), Power Down mode is selected as sleep mode. The AT43USB355 does not support the Idle Mode and SM should always be set to one when entering the Sleep Mode. ...
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... The microcontroller's firmware should take the embedded function out of the suspended state. USB hardware received a USB bus reset. This applies only in cases where a separation between USB bus reset and microcontroller reset is required. Be very careful when using this feature. AT43USB355 31 ...
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... Control and Status Register are modified by the USB hardware OUT Packet is set (control and OUT end-points Packet Ready is cleared AND TX Complete is set (control and IN end-points SETUP is set (control end-points only Complete is set AT43USB355 ...
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... Bit 0 – FEP0 IMSK: End-point 0 Interrupt Mask When the FE0 IMSK bit is set (1), the Function End-point 0 Interrupt is masked. 2603G–USB–04/ SOF IMSK EOF2 IMSK – FEP3 IMSK R/W R AT43USB355 HEP0 IMSK FEP2 IMSK FEP1 IMSK FEP0 IMSK R/W R/W R/W R UIMSKR 0 33 ...
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... Bit 1 – FEP1 INTACK: Function End-point 1 Interrupt Acknowledge The microcontroller firmware writes this bit to clear the FEP1 bit. • Bit 0 – FEP0 INTACK: Function End-point 0 Interrupt Acknowledge The microcontroller firmware writes this bit to clear the FEP0 INT bit. AT43USB355 ...
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... SOF IE EOF2 IE – FEP3 IE R/W R – – – – AT43USB355 HEP0 IE FEP2 IE FEP1 IE FEP0 IE R/W R/W R BUS INT FRWUP RSM GLB SUSP R UIER R/W ...
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... These bits are reserved and are always read as zeros. • Bit 3 – BUS INT MSK: USB Reset Interrupt Mask • Bit 2 – FRWUP MSK: Function Remote Wakeup Interrupt Mask • Bit 1 – RSM MSK: Resume Interrupt Mask • Bit 0 – GLB SUSP MSK: Global Suspend Interrupt Enable AT43USB355 – ...
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... Description for detailed information. Note that the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt routine. This must be handled by software. 2603G–USB–04/06 Bit R/W R/W R AT43USB355 R/W R/W R/W R ...
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... Only an external reset, an external level interrupt on INT0 or INT1, can wake up the MCU. Note that when a level triggered interrupt is used for wake-up from power down, the low level must be held for a time longer than the reset delay time-out period t will fail to wake up. AT43USB355 ...
Page 39
... Timer/Counters The AT43USB355 provides two general-purpose Timer/Counters - one 8-bit T/C and one 16- bit T/C. The Timer/Counters have individual prescaling selection from the same 10-bit prescal- ing timer. Both Timer/Counters can either be used as a timer with an internal clock timebase counter with an external pin connection which triggers the counting. ...
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... Similarly, the high prescaling opportunities make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions. Figure 13. Timer/Counter0 Block Diagram Timer Int. Mask Register (TIMSK) 7 Timer/Counter0 (TCNT0) AT43USB355 40 T/C0 Overflow IRQ Timer Int. Flag Register (TIFR) 0 T/C Clock Source T/C0 Control Register ...
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... Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT43USB355 and always read as zero. • Bits – CS02, CS01, CS00: Clock Select0, bit 2, 1 and 0 The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0. ...
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... Timer/Counter1 Figure 14. Timer/Counter1 Block Diagram T/C1 OVERFLOW IRQ TIMER INT. MASK REGISTER (TIMSK) 15 T/C1 INPUT CAPTURE REGISTER (ICR1) 15 TIMER/COUNTER1 (TCNT1) 15 16-BIT COMPARATOR 15 TIMER/COUNTER1 OUTPUT COMPARE REGISTER A AT43USB355 42 T/C1 COMPARE T/C1 COMPARE MATCHB IRQ MATCHA IRQ TIMER INT. FLAG REGISTER A (TCCR1A) REGISTER (TIFR CAPTURE TRIGGER ...
Page 43
... Input Capture Register - ICR1, triggered by an external event on the Input Capture Pin (ICP/PF3). The actual capture event settings are defined by the Timer/Counter1 Control Register (TCCR1B). The AT43USB355 has no analog comparator and the mux control signal, ACO, is permanently set so that the ICP input is routed to the noise canceler. ...
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... COM1X1 Note: • Bits 3..2 – Res: Reserved Bits These bits are reserved bits in the AT43USB355 and always read zero. • Bits 1..0 – PWM11, PWM10: Pulse Width Modulator Select Bits 1 and 0 These bits select PWM operation of Timer/Counter1 as specified in Table 13. Table 13. PWM Mode Select ...
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... Timer/Counter1 contents are transferred to the ICR1 on the rising edge of the ICP. • Bits 5, 4 – Res: Reserved Bits These bits are reserved bits in the AT43USB355 and always read zero. • Bit 3 – CTC1: Clear Timer/Counter1 on Compare Match When the CTC1 control bit is set (one), the Timer/Counter1 is reset to $0000 in the clock cycle after a compareA match ...
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... The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the 12 MHz system clock. If the external pin modes are used for Timer/Counter1, transitions on PB1/(T1) will clock the counter even if the pin is configured as an output. This feature can give the user SW control of the counting. AT43USB355 46 CS11 CS10 ...
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... Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value. 2603G–USB–04/ MSB – – – – – – – R/W R/W R/W R/W R/W R/W R/W R AT43USB355 – – – – – – – LSB R/W R/W R/W R/W R/W R/W R/W R TCNT1H TCNT1L ...
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... The TEMP register is also used when accessing TCNT1, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program and from interrupt routines if interrupts are allowed from within interrupt routines. AT43USB355 ...
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... Timer TOP value $00FF (255) $01FF (511) $03FF(1023) AT43USB355 – – – – – – – LSB ...
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... Note: If the compare register contains the TOP value and the prescaler is not in use (CS12..CS10 = 001), the PWM output will not produce any pulse at all, because up-counting and down-counting values are reached simultaneously. When the prescaler is in use AT43USB355 50 COM1X0 Effect on OCX1 ...
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... Table 18 for a detailed description. The WDR (Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog reset, the AT43USB355 resets and executes from the reset vector. ...
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... Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the AT43USB355 and will always read as zero. • Bit 4 – WDTOE: Watch Dog Turn-Off Enable This bit must be set (one) when the WDE bit is cleared. Otherwise, the watchdog will not be disabled ...
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... Serial Peripheral The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between Interface (SPI) the AT43USB355 and peripheral devices or between several AVR devices. The AT43USB355 SPI features include the following: • Full-duplex, 3-wire Synchronous Data Transfer • Master or Slave Operation • ...
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... When the SPI is enabled, the data direction of the MOSI, MISO, SCK and SS pins is overrid- den according to the following table: Table 19. SPI Pin Overrides Pin MOSI MISO SCK SSN Note: AT43USB355 54 MISO MISO MASTER LSB MOSI MOSI SCK SCK SS SS ...
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... SCK Cycle # (For Reference) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (From Master) MISO (From Slave) SS (To Slave) Note: * Not defined but normally LSB of character just received. 2603G–USB–04/ MSB MSB AT43USB355 LSB LSB * 55 ...
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... Figure 21. SPI Transfer Format with CPHA = 1 and DORD = 0 SCK Cycle # (For Reference) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (From Master) MISO * (From Slave) SS (To Slave) Note: * Not defined, but normally LSB of previously transmitted character. AT43USB355 MSB MSB ...
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... Table 20. Relationship Between SCK and the Oscillator Frequency 2603G–USB–04/ SPIE SPE DORD R/W R/W R SPR1 SPR0 AT43USB355 MSTR CPOL CPHA SPR1 R/W R/W R/W R SCK Frequency 3 MHz 750 kHz 187.5 kHz 93.75 kHz 0 SPR0 SPCR ...
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... WCOL bit (and the SPIF bit) are cleared (zero) by first reading the SPI Status Register when WCOL is set (one), and then accessing the SPI Data Register. • Bit 5..0 – Res: Reserved Bits These bits are reserved bits in the AT43USB355 and will always read as zero. SPI Data Register – SPDR Bit ...
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... Interrupt on ADC Conversion Complete The AT43USB355 features a 10-bit successive approximation ADC. The ADC is connected to a 12-channel Analog Multiplexer to pins AD0 – AD11. The ADC contains a Sample and Hold Amplifier that ensures that the input voltage to the ADC is held at a constant level during con- version ...
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... The ADC has its own interrupt that can be triggered when a conversion completes. When ADC access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if the result is lost. Figure 23. ADC Prescaler AT43USB355 60 SSA pin minus one LSB. The analog input channel is selected by writing to the MUX ...
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... ADSC remains high. Using Free Running Mode and an ADC clock frequency of 1 MHz gives the lowest conversion time with a maximum resolution, 12 µs, equivalent to 83 kSPS. For a summary of conversion times, see Table 21. Figure 24. ADC Timing Diagram, Extended Conversion (Single Conversion Mode) 2603G–USB–04/06 AT43USB355 61 ...
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... Figure 25. ADC Timing Diagram, Single Conversion Figure 26. ADC Timing Diagram, Free Running Conversion Table 21. ADC Conversion Time Sample and Hold (Cycles from Start of Conversion) Condition Normal Conversion AT43USB355 62 Conversion Time (Cycles Conversion Time (µ 768 2603G–USB–04/06 ...
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... Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT43USB355 and always read as zero. • Bits 3..0 – MUX3..MUX0: Analog Channel Select Bits 3-0 The value of these three bits selects which analog input ADC11..0 is connected to the ADC. ...
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... When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Complete interrupt is activated. • Bits 2..0 – ADPS2..ADPS0: ADC Prescaler Select Bits These bits determine the division factor between the 2 MHz frequency and the input clock to the ADC. AT43USB355 ...
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... ADPS1 – – – ADC7 ADC6 ADC5 AT43USB355 ADPS0 Division Factor – – – ADC9 ADC4 ADC3 ADC2 ADC1 ...
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... In the AT43USB355E, Port F[0:4] are used as the SPI signals for the external serial EEPROM. Once the data from the SEEPROM are loaded to the SRAM, Port F[1:3] become available as GPIO pins. Only cycling the power to the chip off and on again will temporarily assign these pins as SEEPROM interface signals ...
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... DDA7 DDA6 DDA5 R/W R/W R PINA7 PINA6 PINA5 N/A N/A N/A PORTAn I Input 0 1 Input 1 0 Output 1 1 Output n: 7,6...0, pin number. AT43USB355 PORTA4 PORTA3 PORTA2 PORTA1 R/W R/W R/W R DDA4 DDA3 DDA2 DDA1 R/W R/W R/W R PINA4 ...
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... The Port B pins with alternate functions are shown in the following table: Table 25. Port B Pins Alternate Functions Port Pin When the pins are used for the alternate function the DDRB and PORTB register has to be set according to the alternate function description. AT43USB355 68 Alternate Functions PB0 T0 (Timer/Counter 0 External Counter Input) ...
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... DDB7 DDB6 DDB5 R/W R/W R PINB7 PINB6 PINB5 N/A N/A N/A PORTBn I Input 0 1 Input 1 0 Output 1 1 Output n: 7, 6...0, pin number. AT43USB355 PORTB4 PORTB3 PORTB2 PORTB1 R/W R/W R/W R DDB4 DDB3 DDB2 DDB1 R/W R/W R/W R ...
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... The Port D Input Pins address (PIND) is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is read, and when reading PIND, the logical values present on the pins are read. AT43USB355 70 Port Pin ...
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... Table 28. DDDn Bits on Port D Pins DDDn Note: 2603G–USB–04/06 PORTDn I Input 0 1 Input 1 0 Output 1 1 Output n: 7, 6...0, pin number. AT43USB355 Comment Tri-state (Hi-Z) PDn will source current if ext. pulled low. Push-Pull Zero Output Push-Pull One Output 71 ...
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... Port F In the AT43USB355 Port F[1: 3-bit bi-directional I/O. Its output buffers can sink or source 2 mA Three I/O memory address locations are allocated for the Port F, one each for the Data Register (PORTF), $06($26), Data Direction Register (DDRF), $05($25) and the Port F Input Pins (PIND), $04($24). The Port F Input Pins address is read only, while the Data Register and the Data Direction Register are read/write ...
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... PortF as General PFn, General I/O Pin: In the AT43USB355E, after firmware downloading, the DDFn bit in the Digital I/O DDRF register selects the direction of this pin. If DDFn is set (one), PFn is con-figured as an output pin. If DDFn is cleared (zero), PFn is configured as an input pin. If PORTFn is set (one) when the pin is configured as an input pin, the MOS pull-up resistor is activated ...
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... CPU. It initiates interrupts and acts upon commands sent by the firmware. The USB function hardware of the AT43USB355 makes the physical interface and the proto- col layer transparent to the user. To start the process, the firmware must first enable the end- points and which place them in receive mode by default ...
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... ANY STABLE STATE RX_SETUP_INT Setup Response RX_OUT_INT TX_COMPLETE_INT Control Write Data Response RX_OUT_INT TX_COMPLETE_INT TX_COMPLETE_INT Control Control Write Status Read Status Response Response Idle AT43USB355 Data Status Stage Stage … OUT(0) OUT(0/1) IN(1) IN(1) DATA0 DATA0/1 DATA1(0) IN(0) … IN(0/1) OUT(1) DATA0 DATA0/1 DATA1(0) Legend: DATAn Data packet with PID’ ...
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... The following information describes how the AT43USB355’s USB hardware and firmware operates during a control transfer between the host and the hub’s or function’s control end- point. Legend: Idle State This is the default state from power-up. Setup Response State The Function Interface Unit (FIU) receives a SETUP token with 8 bytes of data from the Host. ...
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... Hardware Hardware DATA0/DATA1 Packet Ready = 0, send NAK Set TX Complete → INT Repeat steps 1 through 8 AT43USB355 Firmware 5. Read UISR 6. Read CSR0 7. If SET ADDRESS, program the new Address, set ADD_EN bit 8. Clear TX_COMPLETE, clear Data End, set Force STALL in CAR0 9 ...
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... FIU places the incoming data into the FIFO, issues an ACK to the host, and asserts an RX_OUT interrupt. 1. OUT token from Host 2. Put DATA0/DATA1 into FIFO 3. ACK to Host 4. Set RX OUT → INT AT43USB355 78 Hardware 4. Read UISR 5. Read CSR0 6. Clear RX OUT, set Data End, set Force Stall in H/FCAR0 ...
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... TX_COMPLETE interrupt token from Host 2. Send DATA1(0) 3. ACK from Host 4. Set TX Complete → INT 2603G–USB–04/06 Hardware 5. Read UISR 6. Read CSR0 7. Clear TX COMPLETE, clear Data 8. Set UIAR[EP0 INTACK] to clear the AT43USB355 Firmware End, set Force STALL in CAR0 interrupt source 79 ...
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... FIU places the incoming data into the FIFO, issues an ACK to the host, and asserts an RX_OUT interrupt. 1. Read UISR 2. Read FCSR1/2/3 3. Read FIFO 4. Clear RX_OUT If more data: Wait for RX_OUT interrupt If no more data: set DATA END 5. Set UIAR[FEP1/2/3 INTACK] to clear the interrupt source AT43USB355 80 2603G–USB–04/06 ...
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... Initial Value • Bit 7 – SAEN: Single Address Enable The Single Address Enable bit allows the microcontroller to configure the AT43USB355 into a single address or a composite device. Once this capability is enabled, the hub end-point 0 (HEP0) is converted from a control end-point to a programmable function end-point FEP3; all the end-points would then operate on the single address. • ...
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... Disable end-point 1 = Enable end-point • Bit 6..4 – Reserved These bits are reserved in the AT43USB355 and will read as zero. • Bit 3 – DTGLE: Data Toggle Identifies DATA0 or DATA1 packets. This bit will automatically toggle and requires clearing by the firmware only in certain special circumstances. ...
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... Disable end-point 1 = Enable end-point • Bit 6..4 – Reserved These bits are reserved in the AT43USB355 and will read as zero. • Bit 3 – DTGLE: Data Toggle Identifies DATA0 or DATA1 packets. This bit will automatically toggle and requires clearing by the firmware only in certain special circumstances. ...
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... Read/Write Initial Value • Bit 7...4 – Reserved These bits are reserved in the AT43USB355 and will read as zero. • Bit 3 – P3 SC: Port 3 Status Change • Bit 2 – P2 SC: Port 2 Status Change • Bit 1 – P1 SC: Port 1 Status Change • Bit 0 – H SC: Hub Status Change ...
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... Function EP1 $1FCC Function EP2 $1FCB Function EP3 $1FCA Read/Write Initial Value • Bit 7..6 – Reserved These bits are reserved in the AT43USB355 and will read as zero. • Bit 5..0 – BYTCT5..0: Byte Count – Length of End-point Data Packet 2603G–USB–04/06 Bit – ...
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... Read/Write Initial Value • Bit 7..4 – Reserved These bits are reserved in the AT43USB355 and will read as zero. • Bit 3 – STALL SENT The USB hardware sets this bit after a STALL has been sent to the host. The firmware uses this bit when responding to a Get Status[End-point] request read only bit and that is cleared indirectly by writing a one to the STALL_SENT_ACK bit of the Control and Acknowl- edge Register ...
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... TX DATA FORCE DIR PACKET END STALL READY TX DATA FORCE DIR PACKET END STALL READY R/W R/W R/W R AT43USB355 STALL_ RX_ RX_OUT_ TX_ SENT_ SETUP_ PACKET_ COMPLETE_ ACK ACK ACK ACK STALL_ RX_ RX_OUT_ TX_ SENT_ SETUP_ PACKET_ COMPLETE_ ACK ...
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... Read/Write Initial Value • Bit 7..4 – Reserved These bits are reserved in the AT43USB355 and will read as zero. • Bit 3 – STALL SENT The USB hardware sets this bit after a STALL has been sent to the host. The firmware uses this bit when responding to a Get Status[End-point] request read only bit and that is cleared indirectly by writing a one to the STALL_SENT_ACK bit of the Control and Acknowl- edge Register ...
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... Read/Write Initial Value • Bit 7 – Reserved This bit is reserved in the AT43USB355 and will read as zero. • Bit 6 – DATA END When set firmware, this bit indicate that the microcontroller has either placed the last data packet in FIFO, or that the microcontroller has processed the last data packet it expects from the Host. • ...
Page 90
... The first two tasks of the Hub Controller are similar to that of a USB function and will not be described in detail in the following section. The descriptions will cover the features of the AT43USB355's hub and how to program it to make a USB-compliant hub. Control transactions for the Hub Control End-point proceed exactly the same way as those described for the embedded function ...
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... Initial Value • Bit 7...5 – Reserved Bits These bits are reserved in the AT43USB355 and will read as zeros. • Bit 4 – SUSP FLG: Suspend Flag This bit is set to 1 while the USB hardware is in the suspended state. This bit is a firmware read only bit set and cleared by the USB hardware. • ...
Page 92
... Hub Status Register In the AT43USB355 overcurrent detection and port power switch control output processing is done in firmware. The hardware is designed so that various types of hubs are possible just through firmware modifications. 1. Hub local power status, bits 0 and 2, are optional features and apply to hubs that report on a global basis ...
Page 93
... Read/Write Initial Value • Bit 7 – Reserved This bits is reserved in the AT43USB355 and will read as zero. • Bit 6..4 – HPCON2..0: Hub Port Control Command These bits are written by firmware to control the port states upon receipt of a Host request. Disable Port = ClearPortFeature(PORT_ENABLE) Action: USB hardware places addressed port in disabled state ...
Page 94
... The ports can also exit from the suspended state through a remote wakeup if this feature is enabled. For Ports 2:3, this means detection of a connect/disconnect or an upstream directed signaling. Remote wakeup for the embedded function is initiated through an external interrupt at INT0. AT43USB355 94 Bit2 Bit1 ...
Page 95
... Port3 $1FBA Read/Write Initial Value • Bit 7 – Reserved This bit is reserved in the AT43USB355 and will read as zero. • Bit 6 – LSP: Low-speed Device Attached 0 = Full-speed device attached to this port 1 = Slow-speed device attached to this port Set to 0 for Port 1 (full-speed only). Set and cleared by the hardware upon detection of device at EOF2. • ...
Page 96
... These registers contain the state of the ports’ DP and DM pins, which will be sent to the host upon receipt of a GetBusState request. • Bit 7..2 – Reserved These bits are reserved in the AT43USB355 and will read as zero. • Bit 1 – DPSTATE: DPlus State Value last EOF. Set and cleared by hardware at EOF2. ...
Page 97
... Except for bit 3, the Port Overcurrent Indicator Change, the bits in this register are set by the USB hardware. Otherwise, the firmware should only clear these bits. • Bit 7..5 – Reserved These bits are reserved in the AT43USB355 and will read as zero. • Bit 4 – RSTSC: Port Reset Status Change change ...
Page 98
... The AT43USB355 is capable of detecting overcurrent during active operation only, or during any condition even when the hub is in the suspended state. When overcurrent in the active state only is desired, any GPIO pin of the AT43USB355 can be used to sense and the over- current condition. Control of the condition must be performed by the firmware. If overcurrent detection under any condition is desired, then specific GPIO pins must be used to sense the overcurrent and the proper bit(s) of UOVCER set ...
Page 99
... BUS_POWER GND Suspend and The AT43USB355 enters suspend only when requested by the USB host through bus inactiv- ity for at least 3 ms. The USB hardware would detect this request, sets the GLB_SUSP bit of Resume SPRSR, Suspend/Resume Register, and interrupts the microcontroller if the interrupt is enabled ...
Page 100
... Finally, the hardware asserts the GLB_SUSP interrupt. 2. Global suspend signaling detected 3. Stop downstream signaling 4. Set GBL SUS bit → interrupt 10. SLEEP bit detected 11. Shut off oscillator AT43USB355 100 Hardware 1.Host stops sending packets 5. Shut down any peripheral activity 6. Set Sleep Enable and Sleep Mode bits of MCUCR 7 ...
Page 101
... Hardware 1.Host resumes signaling Hardware detected Hardware 1.External event activates INT0/INT1 interrupt AT43USB355 Firmware 6. Reset RSM and GBL SUSP bits 7. Restore GPIO states if required 8. Clear UOVCER bit 2 9. Enable peripheral activity Firmware 5. Reset RSM and GBL SUSP bits 6 ...
Page 102
... Downstream Ports 3. Suspend or resume port per command Selective Suspend, Embedded Function Selective Resume, Embedded Function 6. Send updated port status at next IN to end-point1 AT43USB355 102 Hardware 1. Set or Clear Port Feature PORT_SUSPEND decoded 2. Write HPCON[2:0] and HPADD[2:0] bits Hardware 1. Set Port Feature PORT_SUSPEND decoded 2. Disable Port 1’ ...
Page 103
... Input Level High (floating) Input Level Low Differential Input Sensitivity DPx and DMx Differential Common Mode Range RL of 1.5 kΩ Static Output Low to 3. kΩ to Static Output High GND Output Signal Crossover Input Capacitance AT43USB355 Condition Min Max VCEXT+0.3 -0.3V 4.6 max VCEXT+0.3 -0.3 4.6 max -40 +125 -65 +150 ...
Page 104
... CSS t CSH AT43USB355 104 Parameter Condition Output Low Level, PA, PB, IOL = 2 mA PD, PF[1:3] Output High Level IOH = 2mA Input Low Level Input High Level PC Pull-up resistor current Input/Output capacitance 1 MHz VCEXT is the voltage of CEXT1, CEXT2, CEXT3 and CEXTA. ...
Page 105
... MOSI HI-Z MISO V OL Parameter Condition Rise time C Fall time C TR/TF matching (1) Driver output resistance Steady state drive 1. With external 27Ω series resistor. TxD+ TxD AT43USB355 t CSH Min = ...
Page 106
... TJR2 For Paired Transitions TFEOPT Source SEO interval of EOP TFEOPR Receiver SEO interval of EOP Width of SEO interval during differential TFST transition Note: 1. With 6.000 MHz, 100 ppm crystal. AT43USB355 106 Parameter Condition Rise time CL = 200 - 600 pF Fall time CL = 200 - 600 pF TR/TF matching R S ...
Page 107
... T PERIOD Point Extended Differential Data Lines Diff. Data-to- SE0 Skew N PERIOD DEOP T PERIOD Differential Data Lines T JR Consecutive Transitions N PERIOD Consecutive N*T AT43USB355 + T XJR2 Source EOP Width: T FEOPT T LEOPT Receiver EOP Width: T FEOPR T LEOPR T T JR1 JR2 JR1 Transitions + T PERIOD JR1 107 ...
Page 108
... TFHESK Table 40. Hub Timings, Low-speed Operation Symbol TLHDD TLHDJ1 TLHDJ2 TLUHJ1 TLUHJ2 TSOP TLEOPD TLHESK AT43USB355 108 Parameter Condition Hub Differential Data Delay without cable Hub Diff Driver Jitter to Next Transition for Paired Transitions Data Bit Width Distortion after SOP Hub EOP Delay Relative ...
Page 109
... Time to evaluate device speed after reset Time to detect a long K from upstream Time to detect a long SEO from upstream Duration of repeating SEO upstream Duration of sending SEO upstream after EOF1 AT43USB355 Min Max Unit 2.5 2000 µs 2.5 2000 µs 2.5 12000 100 µ ...
Page 110
... Data Lines Downstream Hub Delay With Cable Figure 35. Hub EOP Delay and EOP Skew Upstream End of Cable V SS Downstream Port Upstream EOP Delay with Cable AT43USB355 110 Downstream Port 50% Point of Initial Swing V SS Hub Delay Crossover Upstream Downstream Point Port T ...
Page 111
... Ordering Code SRAM AT43USB355E-AC Mask ROM AT43USB355M-AC SRAM AT43USB355E-AU Mask ROM AT43USB355M-AU 2603G–USB–04/06 Package 64 LQFP 64 LQFP 64 LQFP 64 LQFP AT43USB355 Operation Range Commercial (0°C to +70°C) Commercial (0°C to +70°C) Green, Industrial (-40°C to +85°C) Green, Industrial (-40°C to +85°C) 111 ...
Page 112
... LQFP Dimensions in Millimeters and (Inches) Controlling Dimensions: Millimeters JEDEC STANDARD MS-026 ACB PIN 1 ID 0.50(0.020) BSC 0.20(0.008) 0.09(0.003) 2325 Orchard Parkway San Jose, CA 95131 R AT43USB355 112 PIN 1 10.10(0.397) 9.90(0.389) 0˚~7˚ 0.75(0.030) 0.15(0.006) 0.45(0.018) 0.05(0.002) TITLE 64-lead, Low-profile (1.4 mm) Plastic Quad Flat ...
Page 113
... WDR\n WDR\n WDR\n WDR\n out 0x21,r16 " disarm and disable the watchdog, do the following: asm ( "ldi r16,0x18\nldi r17,0x10\n\n out 0x21,r16\n out 0x21,r17 " ); Please note that if the AVR runs at 24 MHz, the WDR should be invoked twenty-six times. 2603G–USB–04/06 AT43USB355 113 ...
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... Bits 2..0 of “ADC Control and Status Register – ADCSR” on page 64 was modified. • Update: The disclaimer and copyright information on the last page was modified. • Additions: Added AT43USB355E-AU and AT43USB355M-AU part numbers to Ordering Information. 2603G–USB–04/06 ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2006. All rights reserved. Atmel trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...