cp3bt13 National Semiconductor Corporation, cp3bt13 Datasheet - Page 38

• Manufacturer Part Number: cp3bt13
• Description: Cp3bt13 Reprogrammable Connectivity Processor With Bluetooth-r And Can Interfaces
• Manufacturer: National Semiconductor Corporation

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DISVRF
IENPROG
PE
PER
MER
The Disable Verify bit controls the automatic
verification feature. This bit must not be
changed while the flash program memory is
busy being programmed or erased.
0
1
The Interrupt Enable for Program bit is clear
after reset. The flash program and data mem-
ories share a single interrupt channel but have
independent interrupt enable control bits.
0
1
The Program Enable bit controls write access
of the CPU to the flash program memory. This
bit must not be altered while the flash program
memory is busy being programmed or erased.
The PER and MER bits must be clear when
this bit is set.
0
1
The Page Erase Enable bit controls whether a
a valid write operation triggers an erase oper-
ation on a 1024-byte page of flash memory.
Page erase operations are only supported for
the main blocks, not the information blocks. A
page erase operation on an information block
is ignored and does not alter the information
block. When the PER bit is set, the PE and
MER bits must be clear. This bit must not be
changed while the flash program memory is
busy being programmed or erased.
0
1
The Module Erase Enable bit controls wheth-
er a valid write operation triggers an erase op-
eration on an entire block of flash memory. If
an information block is written in this mode,
both the information block and its correspond-
ing main block are erased. When the MER bit
is set, the PE and PER bits must be clear. This
bit must not be changed while the flash pro-
gram memory is busy being programmed or
erased.
0
1
–
–
–
–
–
–
–
–
–
–
New flash program memory contents are
automatically verified after programming.
Automatic verification is disabled.
No interrupt request is asserted to the
ICU when the FMFULL bit is cleared.
An interrupt request is made when the
FMFULL bit is cleared and new data can
be written into the write buffer.
Programming the flash program memory
by the CPU is disabled.
Programming the flash program memory
is enabled.
Page erase mode disabled. Write opera-
tions are performed normally.
A valid write operation to a word location
in program memory erases the page that
contains the word.
Module erase mode disabled. Write oper-
ations are performed normally.
A valid write operation to a word location
in a main block erases the block that con-
tains the word. A valid write operation to a
word location in an information block
erases the block that contains the word
and its associated main block.
38
8.5.7
This register reports the currents status of the on-chip Flash
memory. The FLSR register is clear after device reset. The
CPU bus master has read/write access to this register.
EERR
PERR
FMBUSY
FMFULL
7
Reserved
Flash Memory Status Register (FMSTAT/
FSMSTAT)
5
The Erase Error bit indicates whether an error
has occurred during a page erase or module
(block) erase. After an erase error occurs,
software can clear the EERR bit by writing a 1
to it. Writing a 0 to the EERR bit has no effect.
Software must not change this bit while the
flash program memory is busy being pro-
grammed or erased.
0
1
The Program Error bit indicates whether an
error has occurred during programming. After
a programming error occurs, software can
clear the PERR bit by writing a 1 to it. Writing
a 0 to the PERR bit has no effect. Software
must not change this bit while the flash pro-
gram memory is busy being programmed or
erased.
0
1
The Flash Memory Busy bit indicates whether
the flash memory (either main block or infor-
mation block) is busy being programmed or
erased. During that time, software must not
request any further flash memory operations.
If such an attempt is made, the CPU is
stopped as long as the FMBUSY bit is active.
The CPU must not attempt to read from pro-
gram memory (including instruction fetches)
while it is busy.
0
1
The Flash Memory Buffer Full bit indicates
whether the write buffer for programming is
full or not. When the buffer is full, new erase
and write requests may not be made. The
IENPROG bit can be enabled to trigger an in-
terrupt when the buffer is ready to receive a
new request.
0
1
DERR FMFULL FMBUSY PERR EERR
–
–
–
–
–
–
–
–
4
The erase operation was successful.
An erase error occurred.
The programming operation was suc-
cessful.
A programming error occurred.
Flash memory is ready to receive a new
erase or programming request.
Flash memory busy with previous erase
or programming operation.
Buffer is ready to receive new erase or
write requests.
Buffer is full. No new erase or write re-
quests can be accepted.
3
2
1
0