z86e72 ZiLOG Semiconductor, z86e72 Datasheet - Page 74
z86e72
Manufacturer Part Number
z86e72
Description
Otp Microcontroller
Manufacturer
ZiLOG Semiconductor
Datasheet
1.Z86E72.pdf
(102 pages)
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Z86E72/73
OTP Microcontroller
70
Stop-Mode Recovery Delay Select (D5)
This bit, if low, disables the 5 ms /RESET delay after Stop-Mode Recovery. The
default configuration of this bit is one. If the “fast” wake up is selected, the Stop-
Mode Recovery source needs to be kept active for at least 5TpC.
Stop-Mode Recovery Edge Select (D6)
A 1 in this bit position indicates that a High level on any one of the recovery
sources wakes the Z86E7X from STOP Mode. A 0 indicates Low level recovery.
The default is 0 on POR.
Cold or Warm Start (D7)
This bit is set by the device upon entering STOP Mode. It is a read-only Flag bit. A
1 in D7 (warm) indicates that the device awakes from a SMR source or a WDT
while in STOP Mode. A 0 in this bit (cold) indicates that the device is reset by a
POR or WDT while not in STOP Mode.
PS008704-0507