ml67q5003 Oki Semiconductor, ml67q5003 Datasheet

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ml67q5003

Manufacturer Part Number
ml67q5003
Description
32-bit Arm -based General Purpose Microcontrollers Ml675k Seriesml675001/ml67q5002/ml67q5003 32-bit Arm -based General Purpose Microcontrollers
Manufacturer
Oki Semiconductor
Datasheet

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Data Sheet
April 2004, Rev 2.0
Description
The Oki ML675001, ML67Q5002, and ML67Q5003 family of
microcontrollers (MCUs) are the newest members of an
extensive and growing family of 32-bit ARM
dard products for general-purpose applications that require
32-bit CPU performance and the low cost afforded by MCU
integrated features.
The ML675001, ML67Q5002 and ML67Q5003 devices each
provide 8 KBytes of unified cache memory, 32 KBytes of
built-in SRAM, 4 KBytes of built-in boot ROM, and a host of
other useful peripherals such as auto-reload timers, a watch-
dog timer (WDT), two pulse-width modulators (PWM), A/D
converters, multiple SIOs, synchronous serial port, I
interface, GPIOs, DMA controller, external memory controller,
and boundary scan capability. In addition, the ML67Q5002
and ML67Q5003 devices offer 256 KBytes and 512 KBytes of
built-in Flash memory respectively. The ML675001,
ML67Q5002 and ML67Q5003 devices are pin-for-pin com-
patible with each other, and are pin-to-pin compatible with
Features
• ARM7TDMI 32-bit RISC CPU
• 32-bit mode (ARM) and/or 16-bit mode (Thumb)
• Built-in external memory controller supports glue-
• Built in Flash ROM
• 32-KBytes built in zero-wait-state SRAM
• 28 Interrupt sources
ML675001/Q5002/Q5003 MCUs
ML675001
ML67Q5002
ML67Q5003
- 16-bit Thumb™ instruction set for power efficiency
less connectivity to memory (including SDRAM and
EDO DRAM) and I/O
- 256 KB (ML67Q5002)
- 512 KB (ML67Q5003)
Part Number
applications
32-Bit ARM
Clock Frequency
60 MHz
60 MHz
60 MHz
®
-Based General Purpose Microcontrollers
ML675001/ML67Q5002/ML67Q5003
®
-based stan-
ML675K Series
Built-in Flash Size
2
(128K x 16-bits)
(256K x 16 bits)
C serial
256 KB
512 KB
None
the Oki ML675001/Q5002/Q5003 family of microcontrollers
for easy performance updates.
The ARM7TDMI
The ML675001/5002/Q5003 family of low-cost ARM-based
MCUs offers system designers a bridge from 8- and 16-bit
proprietary MCU architectures to ARM’s higher-performance,
affordable, widely-accepted industry standard architecture
and its industry-wide support infrastructure. The ARM indus-
try infrastructure offers the system developers many
advantages including software compatibility, many ready-to-
use software applications, large choices among hardware
and software development tools. These ARM-based advan-
tages allow Oki’s customers to better leverage engineering
resources, lower development costs, minimize project risks,
and reduce their product time to market. In addition, migra-
tion of a design with an Oki standard MCU to an Oki custom
solution is easily facilitated with its award-winning µPLAT™
product development architecture.
• DMA: Two channels with external access
• Timers: Seven 16-bit timers
• Watch-Dog Timer: dual-stage 16 bit
• PWM: Two 16-bit channels
• Serial Interfaces: SIO, UART, SSIO, I
• GPIO: 42 bits
• A/D Converter: Four 10-bit channels
• Built-in boot ROM accommodates in-circuit Flash
• Packages
ROM re-programming and field-updates
- 144-pin plastic LQFP
- 144-pin plastic LFBGA
144-pin plastic LQFP (ML675001TC)
144-pin plastic LFBGA (ML675001LA)
144-pin plastic LQFP (ML67Q5002TC)
144-pin plastic LFBGA (ML67Q5002LA)
144-pin plastic LQFP (ML67Q5003TC)
144-pin plastic LFBGA (ML67Q5003LA)
®
Advantage
Packages
2
C

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ml67q5003 Summary of contents

Page 1

... SIOs, synchronous serial port, I interface, GPIOs, DMA controller, external memory controller, and boundary scan capability. In addition, the ML67Q5002 and ML67Q5003 devices offer 256 KBytes and 512 KBytes of built-in Flash memory respectively. The ML675001, ML67Q5002 and ML67Q5003 devices are pin-for-pin com- ...

Page 2

... PLLGND AVDD AGND DRAME_N TEST TEST1 BSEL[1:0] FWR JSEL 2 • Oki Semiconductor April 2004, Rev 2.0 Internal (MCP) FLASH ROM ML67Q5002: 256KB ML67Q5003: 512KB µPLAT-7D TIC External Memory Boot ROM DRAMC Controller 4KB APB Bridge IRC Exp. IRC AMBA APB Bus System ...

Page 3

... JTAG interface, break point register function: Built-in Memory FLASH ROM: ML675001: ROM-less version ML67Q5002: 256 Kbytes (128K x 16 bits) ML67Q5003: 512 Kbytes (256K x 16 bits) Access timing of this FLASH memory is configured by the ROM bank control register of the external memory controller. SRAM: 32KB (8K x 32bits) ...

Page 4

... ML675001/ML67Q5002/ML67Q5003 Direct Memory Access Controller Two DMA channels that transfer data between: • Memory and memory • I/O and memory • I/O and I/O. 1. Number of 2 channels channels: 2. Channel priority Fixed mode: Channel priority level is always level: fixed (channel 0 >1). Roundrobin: Priority level of the channel requested for transfer is kept lowest ...

Page 5

... Chip erase time: 100 msec 8. Write protection - Block protect: top address 8Kwords can be protected - Chip protect: all words can be protected 9. Number of commands: 9 10. Highly reliable read/program - Sector programming: 1,000 times Data hold period: 10 years April 2004, Rev 2.0 ML675001/ML67Q5002/ML67Q5003 Oki Semiconductor • 5 ...

Page 6

... ML675001/ML67Q5002/ML67Q5003 Pin Configuration PIOD[6]/ XIOCS_N XIOCS_N XDQM[1] [3] [1] PIOD[7]/ XIOCS_N XIOCS_N XDQM[0] [2] [0] PIOB[1]/ PIOB[2]/ PIOB[0]/ DREQCL DREQ[1] DREQ[0] R[0] PIOB[3]/ PIOB[5]/ VDD_IO DREQCLR[ TCOUT 1] [1] PIOC[0]/ PIOB[4]/ GND PWMOUT[ TCOUT 0] [0] XBS_N XBS_N PIOD[0]/ [0] [1] XWAIT PIOD[2]/ PIOD[1]/ VDD_IO XRAS_N ...

Page 7

... SCL / PIOE[4] 143 STXD / PIOB[6] 144 Notes: 1. For pins that have multiple functions, the primary function is the name closest to the package. 2. Leave NC pins unconnected. 144-Pin LQFP (TOP VIEW) Figure 2. 144-Pin Plastic LQFP April 2004, Rev 2.0 ML675001/ML67Q5002/ML67Q5003 72 XIOCS_N[3] 71 XIOCS_N[2] 70 XIOCS_N[1] 69 GND 68 XIOCS_N[0] 67 ...

Page 8

... ML675001/ML67Q5002/ML67Q5003 List of Pins Pin Primary Function LQFP BGA Symbol I TEST1 – Test mode input 2 B1 PIOB[7] I/O General port (with interrupt function FWR I Test mode input 4 C1 RESET_N I Reset input 5 D3 VDD_IO VDD IO power supply 6 C2 XD[0] I/O External data bus 7 D1 ...

Page 9

... XDQM[1]/XCAS_N[1] XDQM[0]/XCAS_N[0] DREQ[0] DREQCLR[0] – DREQ[1] DREQCLR[1] TCOUT[0] TCOUT[1] PWMOUT[0] PWMOUT[1] – – – – XWAIT XCAS_N April 2004, Rev 2.0 ML675001/ML67Q5002/ML67Q5003 Secondary Function I/O Description – – – – – – O External address output – O External address output O External address output O External address output – ...

Page 10

... ML675001/ML67Q5002/ML67Q5003 List of Pins (Continued) Pin Primary Function LQFP BGA Symbol I/O 90 G10 GND GND GND 91 G11 VDD_IO VDD I/O power supply 92 G13 PIOD[2] I/O General port (with interrupt function) 93 F11 PIOD[3] I/O General port (with interrupt function) 94 F10 PIOD[4] I/O General port (with interrupt function) 95 F12 ...

Page 11

... I/O General port (with interrupt function) Description Symbol DSR DCD – DTR RTS RI – SDA SCL STXD April 2004, Rev 2.0 ML675001/ML67Q5002/ML67Q5003 Secondary Function I/O Description I UART Set Ready I UART Carrier Detect – O UART Data Terminal Ready O UART Request To Send I UART Ring Indicator – ...

Page 12

... ML675001/ML67Q5002/ML67Q5003 Pin Descriptions Pin Name I/O System RESET_N I Reset input BSEL[1:0] I Boot device select signal. BSEL[ The selected device is mapped to BANK0 (0x0000_0000 - 0x07FF_FFFF) after reset. CLKMD[1:0] I Clock mode inputs. Normally connected to GND. OSC0 I Crystal oscillator connection or external clock input. If used, connect a crystal oscillator (5 MHz to 14 MHz) to OSC0 and OSC1_N. ...

Page 13

... Indicates that UART is ready to establish a communications link with the modem or data set. Bit 0 in the modem control register controls this output. RTS O Request To Send. indicates that UART is ready to transfer data to modem or data set. Bit 1 in the modem con- trol register controls this output. ML675001/ML67Q5002/ML67Q5003 Description April 2004, Rev 2.0 Primary/ Secondary Logic – ...

Page 14

... ML675001/ML67Q5002/ML67Q5003 Pin Descriptions (Continued) Pin Name I Ring Indicator. Indicates that the modem or data set has received a telephone ring indicator. Bit 6 in the modem status register reflects this input. SIO Interface STXD O SIO transmit signal. SRXD I SIO receive signal Interface ...

Page 15

... DD_CORE V = 3.0 to 3.6 V DD_IO — = -40 to +85°C) A Conditions — -100 µ 100 µ ML675001/ML67Q5002/ML67Q5003 Rating Unit -0.3 to +3.6 -0.3 to +4.6 -0.3 to +3.6 -0 +0.3 DD_IO -0 +0.3 DD_IO -0 +0.3 DD_IO -0 0.3) and -0.3 to (AV + 0.3) DD_IO DD -0 REF -10 to +10 mA -20 to +20 -30 to +30 ...

Page 16

... ML675001/ML67Q5002/ML67Q5003 DC Characteristics (V = 2. 3 DD_CORE DD_IO Item Symbol [3] Input leakage current [ [ Output leak current, 3-state output in High [3] impedance mode Input pin capacitance C I Output pin capacitance C O I/O pin capacitance C IO Analog reference power supply current ...

Page 17

... Therefore, before performing reflow mounting, contact the Oki’s sales department for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). Figure 3. P-LFBGA144-1111-0.80 Figure 4. LQFP144-P-2020-0.50-K April 2004, Rev 2.0 ML675001/ML67Q5002/ML67Q5003 Oki Semiconductor • 17 ...

Page 18

... Related Oki Documents for the ML675001/Q5002/Q5003 ML674001/2/3 and ML675001/2/3 User’s Manual ML674001/2/3 and ML675001/2/3 Boot Program User’s Manual ML67Q4003 and ML67Q5003 Flash Memory User’s Manual ML674001/2/3 and ML675001/2/3 Power Management User’s Manual ML67Q5003 CPU Board User’s Manual ML67Q5003 Sample Program User’ ...

Page 19

... ML675001/ML67Q5002/ML67Q5003 April 2004, Rev 2.0 Oki Semiconductor • 19 ...

Page 20

... ML675001/ML67Q5002/ML67Q5003 Notice The information contained herein can change without notice owing to product and/ or technical improvements. Please make sure before using the product that the information you are referring to is up-to-date. The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product ...

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