ksz8851-mql Micrel Semiconductor, ksz8851-mql Datasheet - Page 69

• Manufacturer Part Number: ksz8851-mql
• Description: Single-port Ethernet Mac Controller With 8/16-bit Or 32-bit Non-pci Interface
• Manufacturer: Micrel Semiconductor

0xCA – 0xCF: Reserved
Indirect Access Data Low Register (0xD0 – 0xD1): IADLR
This register contains the indirect data (low word) for MIB counter.
Indirect Access Data High Register (0xD2 – 0xD3): IADHR
This register contains the indirect data (high word) for MIB counter.
Power Management Event Control Register (0xD4 – 0xD5): PMECR
This register is used to control the KSZ8851M power management event, capabilities and status.
February 2009
Micrel, Inc.
11-10
9-5
4-0
Bit
15-0
Bit
15-0
Bit
15
14
13
12
11-8
7
Default
-
0
0
0
0x0
0
-
0x0
0x00
Default
0x0000
Default
0x0000
RW
RW
RW
R/W
RW
R/W
RW
R/W
RO
RW
RW
RW
RW
RW
Description
Reserved.
PME Delay Enable
This bit is used to enable the delay of PME output pin assertion.
When this bit is set to 1, the device will not assert the PME output till the device’s all
clocks are running and ready for host access.
When this bit is set to 0, the device will assert the PME output without delay.
This bit is only valid when Auto Wake-Up Enable (bit7) is set to 1 in this register.
Reserved
PME Output Polarity
This bit is used to control the PME output pin polarity.
When this bit is set to 1, the PME output pin is active high.
When this bit is set to 0, the PME output pin is active low.
Wake-on-LAN to PME Output Enable
These four bits are used to enable the PME output pin asserted when one of these wake-
on-LAN events is detected:
Bit 11: is corresponding to receive wake-up frame.
Bit 10: is corresponding to receive magic packet.
Bit 9: is corresponding to link change from down to up.
Bit 8: is corresponding to signal energy detected.
When the bit is set to 1, the PME pin will be asserted when a corresponding wake-on-
LAN event is occurred.
When this bit is set to 0, the PME pin will be not asserted when a corresponding wake-
on-LAN event is occurred.
Auto Wake-Up Enable
1 = Read cycle is enabled (MIB counter will clear after read).
0 = No operation.
Table Select
00 = reserved.
01 = reserved.
10 = reserved.
11 = MIB counter selected.
Reserved.
Indirect Address
Bit 4-0 of indirect address for 32 MIB counter locations.
Description
Indirect Low Word Data
Bit 15-0 of indirect data.
Description
Indirect High Word Data
Bit 31-16 of indirect data.
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KSZ8851-16/32 MQL/MQLI
M9999-021309-1.1