mm908e622 Freescale Semiconductor, Inc, mm908e622 Datasheet - Page 46

• Manufacturer Part Number: mm908e622
• Description: Mm908e622 Integrated Quad Half-bridge, Triple High-side And Ec Glass Driver With Embedded Mcu And Lin For High End Mirror
• Manufacturer: Freescale Semiconductor, Inc

ECF— EC terminal Failure Bit
electrochrome output is present
WINDOW WATCHDOG
recover from e.g. code runaways or similar conditions.
the watchdog clear has not only to occur but to be done at a
certain time frame / window.
Normal mode
mode and is ceased in Stop and Sleep mode. On setting the
WDRE bit, the watchdog functionality is activated. Once this
function is enabled it is not possible to disable it via software.
Reset clears the WDRE bit.
be cleared in the Window Open frame. This is done by writing
a logic “1” to the WDRST bit in the Watchdog Control register
(WDCTL). The actual reset of the watchdog counter occurs at
the end of the corresponding SPI transmission with the rising
edge of the SS signal.
if the timer has reached its end value or if a watchdog reset
(WDRST) has occurred in the closed window.
WDCTL, in order to get 10ms, 20ms, 40ms and 80ms period.
46
908E622
Functional Device Operation
Operational Modes
This read only bit is set if a fail condition on the
The window watchdog is to supervise the device and to
The use of a window watchdog adds additional safety as
The window watchdog function is just available in Normal
To prevent a Watchdog reset, the Watchdog timer has to
If the watchdog is enabled, it will generate a system reset
The watchdog period can be selected with 2 bits in the
1 = EC terminal fail
0 = EC normal operating
no watch dog clear allowed
WD timing x 50%
Figure 30. Window Watchdog Period
Window closed
Figure 29. ECF flag generation
ECOCF
ECOLF
WD period ( timing selected by Bits WDP1:0)
for watch dog clear
WD timing x 50%
ECF
Window open
Stop mode
mode (counter/oscillator stopped). After wake-up the
watchdog timer is automatically cleared in order to give the
MCU the full time to reset the watchdog.
Sleep mode
mode. Due to the reason that the main voltage regulator
asserts an LVR reset the Watchdog functionality is disabled
and the WDRE bit is cleared as soon as sleep mode is
entered. To reenable this function bit WDRE has to be set
after wake-up.
Watchdog Control Register (WDCTL)
WDRE - Watchdog Reset Enable Bit
WDRE can only be set and can’t be cleared by software.
Reset clears the WDRE bit.
WDP1:0 - Watchdog Period Select Bits
Reset clears the WDP1:0 bits.
WDRST - Watchdog Reset Bit
reset the watchdog timer.
Reset
Read
Write
WDP1
Operations of the watchdog function is ceased in stop
Operations of the watchdog function is ceased is sleep
This read/write (write once) bit activates the watchdog The
This read/write bit select the clock rate of the Watchdog.
This write only bit resets the Watchdog. Write a logic [1] to
0
0
1
1
1 = Watchdog enabled
0 = Watchdog disabled
1 = Reset WD and restart timer
0 = no effect
Table 12. Watchdog Period Selection Bits
WDRE
Bit7
Register Name and Address: WDCTL - $0B
0
WDP0
WDP1
0
1
0
1
6
0
WDP0
Analog Integrated Circuit Device Data
5
0
80ms window watchdog period
40ms window watchdog period
20ms window watchdog period
10ms window watchdog period
4
0
0
Freescale Semiconductor
3
0
0
Mode
2
0
0
1
0
0
WDRST
Bit0
0
0