xa3sd3400a Xilinx Corp., xa3sd3400a Datasheet - Page 44

• Manufacturer Part Number: xa3sd3400a
• Description: Xa Spartan-3a Dsp Automotive Fpga Family Data Sheet
• Manufacturer: Xilinx Corp.

Configuration and JTAG Timing
General Configuration Power-On/Reconfigure Timing
X-Ref Target - Figure 10
Table 46: Power-On Timing and the Beginning of Configuration
DS705 (v1.1) January 20, 2009
Product Specification
Notes:
1.
2.
3.
4.
T
T
T
T
T
POR
PROG
PL
INIT
ICCK
(2)
The numbers in this table are based on the operating conditions set forth in
and V
Power-on reset and the clearing of configuration memory occurs during this period.
This specification applies only to the SPI and BPI modes.
For details on configuration, see UG332, Spartan-3 Generation Configuration User Guide.
(2)
Symbol
(3)
Notes:
1.
2.
3.
V
CCAUX
(Open-Drain)
CCO
R
The V
The Low-going pulse on PROG_B is optional after power-on.
The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
PROG_B
V
(Supply)
(Supply)
(Supply)
V
(Output)
Bank 2
CCAUX
lines.
(Input)
INIT_B
CCINT
CCLK
CCINT
The time from the application of V
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
The width of the low-going pulse on the PROG_B pin
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
Minimum Low pulse width on INIT_B output
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
, V
Figure 10: Waveforms for Power-On and the Beginning of Configuration
CCAUX
, and V
CCO
supplies can be applied in any order.
Description
1.0V
2.0V
2.0V
CCINT
T
T
www.xilinx.com
POR
PROG
, V
CCAUX
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
, and V
T
Table
PL
CCO
8. This means power must be applied to all V
T
Device
ICCK
All
All
All
All
All
Min
300
0.5
0.5
-
-
DS705_11_061908
Max
18
2
4
-
-
1.2V
3.3V
2.5V
3.3V
2.5V
or
or
CCINT
Units
ms
ms
, V
μs
ns
μs
CCO
44
,