xc5vlx30 Xilinx Corp., xc5vlx30 Datasheet
xc5vlx30
Manufacturer Part Number
xc5vlx30
Description
Virtex-5 Family Overview
Manufacturer
Xilinx Corp.
Datasheet
1.XC5VLX30.pdf
(13 pages)
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DS100 (v4.3) June 18, 2008
General Description
The Virtex®-5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL™ (Advanced
Silicon Modular Block) column-based architecture, the Virtex-5 family contains four distinct platforms (sub-families), the most choice
offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic
designs. In addition to the most advanced, high-performance logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks,
including powerful 36-Kbit block RAM/FIFOs, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally-
controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles
with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) clock generators, and advanced configuration options.
Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI
Express™ compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance
PowerPC® 440 microprocessor embedded blocks. These features allow advanced logic designers to build the highest levels of
performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5
FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength
of FPGAs. Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance logic designers, high-performance DSP
designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and
connectivity capabilities. The Virtex-5 LXT, SXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction
layer capability.
Summary of Virtex-5 Features
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© 2006–2008 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. The PowerPC
name and logo are registered trademarks of IBM Corp. and used under license therefrom. All other trademarks are the property of their respective owners.
DS100 (v4.3) June 18, 2008
Advance Product Specification
Four platforms LX, LXT, SXT, and FXT
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Cross-platform compatibility
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Most advanced, high-performance, optimal-utilization,
FPGA fabric
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Powerful clock management tile (CMT) clocking
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36-Kbit block RAM/FIFOs
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High-performance parallel SelectIO technology
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Virtex-5 LX: High-performance general logic applications
Virtex-5 LXT: High-performance logic with advanced
serial connectivity
Virtex-5 SXT: High-performance signal processing
applications with advanced serial connectivity
Virtex-5 FXT: High-performance embedded systems with
advanced serial connectivity
LXT, SXT, and FXT devices are footprint compatible in
the same package using adjustable voltage regulators
Real 6-input look-up table (LUT) technology
Dual 5-LUT option
Improved reduced-hop routing
64-bit distributed RAM option
SRL32/Dual SRL16 option
Digital Clock Manager (DCM) blocks for zero delay
buffering, frequency synthesis, and clock phase shifting
PLL blocks for input jitter filtering, zero delay buffering,
frequency synthesis, and phase-matched clock division
True dual-port RAM blocks
Enhanced optional programmable FIFO logic
Programmable
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Built-in optional error-correction circuitry
Optionally program each block as two independent 18-
Kbit blocks
1.2 to 3.3V I/O Operation
Source-synchronous interfacing using ChipSync™
technology
Digitally-controlled impedance (DCI) active termination
Flexible fine-grained I/O banking
High-speed memory interface support
True dual-port widths up to x36
Simple dual-port widths up to x72
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Advanced DSP48E slices
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Flexible configuration options
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System Monitoring capability on all devices
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Integrated Endpoint blocks for PCI Express
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Tri-mode 10/100/1000 Mb/s Ethernet MACs
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RocketIO™ GTP transceivers 100 Mb/s to 3.75 Gb/s
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RocketIO GTX transceivers 150 Mb/s to 6.5 Gb/s
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PowerPC 440 Microprocessors
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65-nm copper CMOS process technology
1.0V core voltage
High signal-integrity flip-chip packaging available in standard
or Pb-free package options
25 x 18, two’s complement, multiplication
Optional adder, subtracter, and accumulator
Optional pipelining
Optional bitwise logical functionality
Dedicated cascade connections
SPI and Parallel FLASH interface
Multi-bitstream support with dedicated fallback
reconfiguration logic
Auto bus width detection capability
On-chip/Off-chip thermal monitoring
On-chip/Off-chip power supply monitoring
JTAG access to all monitored quantities
LXT, SXT, and FXT Platforms
Compliant with the PCI Express Base Specification 1.1
x1, x4, or x8 lane support per block
Works in conjunction with RocketIO™ transceivers
LXT, SXT, and FXT Platforms
RocketIO transceivers can be used as PHY or connect to
external PHY using many soft MII (Media Independent
Interface) options
LXT and SXT Platforms
FXT Platform only
FXT Platform only
RISC architecture
7-stage pipeline
32-Kbyte instruction and data caches included
Optimized processor interface structure (crossbar)
Virtex-5 Family Overview
Advance Product Specification
1
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