ep1c6t144i8es Altera Corporation, ep1c6t144i8es Datasheet - Page 75

• Manufacturer Part Number: ep1c6t144i8es
• Description: Cyclone Fpga Family
• Manufacturer: Altera Corporation

Preliminary Information
Altera Corporation
Preliminary & Final Timing
Timing models can have either preliminary or final status. The Quartus II
software issues an informational message during the design compilation
if the timing models are preliminary.
Cyclone device timing models.
Preliminary status means the timing model is subject to change. Initially,
timing numbers are created using simulation results, process data, and
other known parameters. These tests are used to make the preliminary
numbers as close to the actual timing parameters as possible.
Final timing numbers are based on actual device operation and testing.
These numbers reflect the actual performance of the device under worst-
case voltage and junction temperature conditions.
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis
independent of device density.
device internal timing microparameters for LEs, IOEs, M4K memory
structures, and MultiTrack interconnects.
t
t
t
t
t
t
t
SU
H
CO
LUT
CLR
PRE
CLKHL
Table 40. Cyclone Device Timing Model Status
Table 41. LE Internal Timing Microparameter Descriptions
Symbol
EP1C3
EP1C4
EP1C6
EP1C12
EP1C20
Device
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LE combinatorial LUT delay for data-in to data-out
Minimum clear pulse width
Minimum preset pulse width
Minimum clock high or low time
Tables 41
Preliminary
v
v
v
v
v
Table 40
Parameter
through
Cyclone FPGA Family Data Sheet
shows the status of the
44
describe the Cyclone
Final
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