at40k20al-1dqc ATMEL Corporation, at40k20al-1dqc Datasheet - Page 27

• Manufacturer Part Number: at40k20al-1dqc
• Description: At40k05al 5k - 50k Gates Coprocessor Fpga With Freeram
• Manufacturer: ATMEL Corporation

AC Timing Characteristics – 3.3V Operation
Delays are based on fixed loads and are described in the notes.
Maximum times based on worst case: V
Minimum times based on best case: V
Maximum delays are the average of t
Clocks and Reset Input buffers are measured from a V
Maximum times for clock input buffers and internal drivers are measured for rising edge delays only.
2818F–FPGA–07/06
Cell Function
Global Clocks and Set/Reset
GCLK Input Buffer
FCLK Input Buffer
Clock Column Driver
Clock Sector Driver
GSRN Input Buffer
Global Clock to Output
Fast Clock to Output
Parameter
t
(Maximum)
t
(Maximum)
t
(Maximum)
t
(Maximum)
t
(Maximum)
t
(Maximum)
t
(Maximum)
PD
PD
PD
PD
PD
PD
PD
PDLH
CC
CC
= 3.6V, temperature = 0°C
and t
= 3.0V, temperature = 70°C
Path
pad -> clock
pad -> clock
pad -> clock
pad -> clock
pad -> clock
pad -> clock
pad -> clock
pad -> clock
clock -> colclk
clock -> colclk
clock -> colclk
clock -> colclk
colclk -> secclk
colclk -> secclk
colclk -> secclk
colclk -> secclk
pad -> GSRN
pad -> GSRN
pad -> GSRN
pad -> GSRN
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
clock pad -> out
PDHL
.
IH
of 1.5V at the input pad to the internal V
Device
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
AT40K05AL
AT40K10AL
AT40K20AL
AT40K40AL
AT40KAL Series FPGA
1.1
1.2
1.2
1.4
0.7
0.8
0.8
0.8
0.8
0.9
1.0
1.1
0.5
0.5
0.5
0.5
3.0
3.7
4.3
5.6
8.3
8.4
8.6
8.8
7.9
8.0
8.1
8.3
-1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Rising edge clock
Rising edge clock
Rising edge clock
Rising edge clock
From any pad to Global
Set/Reset network
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
Rising edge clock
Fully loaded clock tree
Rising edge DFF
20 mA output buffer
50 pf pin load
IH
of 50% of V
CC
.
27