z89321 ZiLOG Semiconductor, z89321 Datasheet
z89321
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z89321 Summary of contents
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P P RELIMINARY RODUCT m S PECIFICATION ...
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From Output Under T est + ...
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± ° ° m ± ° ° ± ...
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± ° ° ± ...
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± ° ° ...
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TCY CLOCK DSVALID /DS EASET EA(2:0) Valid Address Out RD//WR EXT(15:0) TCY CLOCK WSET WAIT /DS EA(2:0) RD//WR EXT(15:0) Tr DSHOLD EAHOLD RDHOLD RDSET Data In WHOLD Valid Address Out Data In Tf CPW ...
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TCY CLOCK DSVALID /DS EASET EA(2:0) Valid Address Out EASET RD//WR WRVALID EXT(15:0) DSHOLD EAHOLD EAHOLD WRHOLD Data Out ...
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TCY CLOCK SSET SCLK FSSET FS0, FS1 TXSET TXD 1 RXD CLOCK INT 0,1,2 INTWidth PROGRAM Fetch N –1 ADDRESS EXECUTE 0 1 RXHOLD RXSET TCY INTSET Fetch N Fetch N +1 Execute N –1 Execute N ...
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CLOCK HHOLD HSET HALT TCY CLOCK RSET /RESET RWIDTH INTERNAL RESET EXECUTE Cycle 0 Cycle 1 RD/WR /DS UO0-1 EA0-2 EXT0-15 PA0-15 RAM/ REGISTERS TCY RRISE Cycle 2 Cycle 3 Tri-Stated Tri-Stated Intact* Cycle 4 Cycle 5 Code Execution Access ...
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CLOCK PASET PROGRAM ADDRESS PROGRAM DATA Not Used 512 words DRAM1 DRAM0 TCY Valid Valid PDSET PDHOLD Valid FFFF Not Used 4 Kwords 01FF INT0-INT2 Vect. 0100 RESET Vector 00FF 0000 Valid Valid Valid FFFF INT0-INT2 Vect. 64 Kwords FFFC ...
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DDATA XDATA Register (16) Y Register (16) Multiplier P Register (24) 24 Shift Unit * Bit Right 3 Bits Right MUX No Shift 1 Bit Left 24 DDATA Mult. (24) Shift Unit * 16 ...
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m m ...
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UI1 UI0 SH3 S15 S14 S13 S12 S11 S10 S9 * The output value is the opposite of the status register content UO1 UO0 RPL ...
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Internal 16-Bit Bus 16 EXT7-1 EXT7-1 CODEC Timer Register EXT7-2 Wait-State Register 16 EXT7-2 ...
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EXT5-1 CLKIN 16 EXT5-2 CLKIN CLKIN TXD m Data Bus 16 EXT6-1 CLKIN 16 EXT6-2 CLKIN CONTROL LOGIC RXD 16 m-Law Compression EXT7 EXT7-2 ...
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int1_ fs1 fs0 sclk txd rxd ...
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D15 D14 D13 D12 D11 D10 D9 D8 5-2 D15 D14 D13 D12 D11 D10 D9 D8 6-1 D15 D14 D13 D12 D11 D10 D9 D8 6-2 D15 D14 D13 D12 D11 D10 ...
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EXT7-1 D15 D14 D13 D12 D11 D10 D9 Note: The timer is an up-counter. Example: EXT7-1 = #%x00D OSC = 12.288 MHz, SCLK = 2.048 MHz, FSYNC = 8 kHz EXT7-1 = #%x80F OSC = 12.288 MHz, SCLK = 6.144 ...
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... Z89321/371/391 SCLK FSO FS1 RXD TXD Serial A/D CLKIN Low-Pass Communicate Filter Data Serial Data Out Serial A/D Smoothing CLKIN Filter Serial Data In Communicate Data Analog In Analog Out m ...
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... Z89321 /371 /391 VCC TXD VDD RXD RDD RCE SCLK DC CCI TDD FS1 TDE VLS int1_ fs1 fs0 sclk txd rxd MC145505p 16 1 VAG 15 2 Rx0 14 3 +Tx 10k 13 4 Txl 12 5 – Mu PDI 8 9 VSS GND –5V Analog Out ...
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UO0 SCLK RxD FS1 AD 1876 Anti-Alias Sample Filtered Analog CLK Signal Dout Vin Busy 16-Bit A/D ...
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Audio ³ 1 Out (Right) 600 40k 0.0022mF NPO ³ 1.0 mF Audio + Out (Left) 600 40k 0.0022mF NPO + 10mF 0.1mF SCLK FS0 TxD Mode RxD Setting Ferrite Bead 2 0.1 mF ...
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int1_ fs1 fs0 sclk txd rxd 64 bits transferred ...
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EXT4 D15 D14 D13 D12 D11 D10 D9 * Default State Count Value (Down-Counter) Clock Source 0 Oscillator/2* 1 CODEC Counter Output Count Operation 0 = Disable Enable Counter ...
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... Z89321, 20 MHz, PLCC, 0°C to +70°C, Plastic Standard Flow Environmental Flow T emperature Package Speed Product Number Zilog Prefix ...
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