dsp56852 Freescale Semiconductor, Inc, dsp56852 Datasheet - Page 38
dsp56852
Manufacturer Part Number
dsp56852
Description
56800e 16-bit Digital Signal Controllers Digital Signal Controller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.DSP56852.pdf
(48 pages)
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4.12 JTAG Timing
38
Operating Conditions: V
TCK frequency of operation
TCK cycle time
TCK clock pulse width
TMS, TDI data setup time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO tri-state
TRST assertion time
DE assertion time
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For120MHz
operation, T = 8.33 ns
2. TCK frequency of operation must be less than 1/4 the processor rate.
3. Parameters listed are guaranteed by design.
(Input)
TCK
V
M
= V
IL
SS
+ (V
= V
Characteristic
SSIO
IH
Figure 4-27 Test Clock Input Timing Diagram
– V
= V
2
IL
SSA
)/2
V
= 0V, V
IH
Table 4-14 JTAG Timing
DD
56852 Technical Data, Rev. 8
= 1.62-1.98V, V
t
V
V
PW
M
IL
DDIO
= V
DDA
Symbol
t
t
CY
TRST
t
f
t
t
t
t
t
t
PW
OP
CY
DS
DH
DV
DE
TS
= 3.0–3.6V, T
1, 3
t
PW
A
33.3
16.6
Min
DC
V
4T
= –40
35
—
—
3
3
M
°
to +120
°
C, C
Max
30
—
—
—
—
12
10
—
—
Freescale Semiconductor
L
≤
50pF, f
op
MHz
Unit
= 120MHz
ns
ns
ns
ns
ns
ns
ns
ns