adsp-21mod870-100 Analog Devices, Inc., adsp-21mod870-100 Datasheet - Page 13

• Manufacturer Part Number: adsp-21mod870-100
• Description: Internet Gateway Processor
• Manufacturer: Analog Devices, Inc.

When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when the
processor is booting and when RESET is active.
The BGH pin is asserted when the ADSP-21mod870 is ready to
execute an instruction but is stopped because the external bus is
already granted to another device. The other device can release
the bus by deasserting bus request. Once the bus is released, the
ADSP-21mod870 deasserts BG and BGH and executes the
external memory access.
Flag I/O Pins
The ADSP-21mod870 has eight general purpose programmable
input/output flag pins. They are controlled by two memory map-
ped registers. The PFTYPE register determines the direction,
1 = output and 0 = input. The PFDATA register is used to read
and write the values on the pins. Data being read from a pin
configured as an input is synchronized to the ADSP-21mod870’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.
In addition to the programmable flags, the ADSP-21mod870
has five fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1,
and FL2. FL0-FL2 are dedicated output flags. FLAG_IN and
FLAG_OUT are available as an alternate configuration of
SPORT1.
Note: Pins PF0, PF1, PF2 and PF3 are also used for device
configuration during reset.
Instruction Set Description
The ADSP-21mod870 assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of
the processor’s unique architecture, offers the following ben-
efits:
• The algebraic syntax eliminates the need to remember cryptic
• Every instruction assembles into a single, 24-bit word that can
• The syntax is a superset ADSP-2100 Family assembly lan-
• Sixteen condition codes are available. For conditional jump,
• Multifunction instructions allow parallel execution of an
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-21mod870 has on-chip emulation support and an
ICE-Port, a special set of pins that interface to the EZ-ICE.
These features allow in-circuit emulation without replacing the
target system processor by using only a 14-pin connection from
REV. 0
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
execute in a single instruction cycle.
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to utilize on-chip memory and conform to the ADSP-
21mod870’s interrupt vector and reset vector map.
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
–13–
the target system to the EZ-ICE. Target systems must have a
14-pin connector to accept the EZ-ICE’s in-circuit probe, a 14-
pin plug. See the ADSP-2100 Family EZ-Tools data sheet for
complete information on ICE products.
Issuing the “chip reset” command during emulation causes the
DSP processor to perform a full chip reset, including a reset of its
memory mode. Therefore, it is vital that the mode pins are set
correctly PRIOR to issuing a chip reset command from the emu-
lator user interface. As the mode pins share functionality with
PF0:2 (and PF3 on the ADSP-21mod870), it may be necessary
to reset the target hardware separately to insure the proper mode
selection state on emulator chip reset.
If you are using a passive method of maintaining mode informa-
tion (as discussed in the Setting Memory Modes section), it
does not matter that mode information is latched by an emula-
tor reset. However, if you are using the RESET pin as a method
of setting the value of the mode pins, then you must consider
the effects of an emulator reset.
One method of ensuring that the values located on the mode
pins is correct is to construct a circuit like the one shown below.
This circuit will force the value located on the mode A pin
to zero, regardless of whether it latched via the RESET or
ERESET pin.
See the ADSP-2100 Family EZ-Tools data sheet for complete
information on ICE products.
The ICE-Port interface consists of the following ADSP-21mod870
pins:
EBR
EBG
ERESET
These ADSP-21mod870 pins must be connected only to the EZ-
ICE connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-
down resistors. The traces for these signals between the ADSP-
21mod870 and the connector must be kept as short as possible,
no longer that three inches.
The following pins are also used by the EZ-ICE:
BR
BG
The EZ-ICE uses the EE (emulator enable) signal to take control
of the ADSP-21mod870 in the target system. This causes the
processor to use its ERESET, EBR and EBG pins instead of the
RESET, BR and BG pins. The BG output is three-stated. These
signals do not need to be jumper-isolated in your system.
RESET
GND
Figure 12. RESET , ERESET Circuit
EMS
EINT
ECLK
1k
ELIN
ELOUT
EE
ADSP-21mod870
PROGRAMMABLE I/O
ERESET
RESET
MODE A/PFO