adsp-2195mkca-160x Analog Devices, Inc., adsp-2195mkca-160x Datasheet - Page 12

• Manufacturer Part Number: adsp-2195mkca-160x
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-2195
During transfers, the SPI ports simultaneously transmit and
receive by serially shifting data in and out on their two serial
data lines. The serial clock line synchronizes the shifting and
sampling of data on the two serial data lines.
In master mode, the DSP’s core performs the following
sequence to set up and initiate SPI transfers:
1. Enables and configures the SPI port’s operation (data
2. Selects the target SPI slave with an SPIxSELy output
3. Defines one or more DMA descriptors in Page 0 of I/O
4. Enables the SPI DMA engine and specifies transfer
5. In non-DMA mode only, reads or writes the SPI port
In slave mode, the DSP’s core performs the following
sequence to set up the SPI port to receive data from a master
transmitter:
1. Enables and configures the SPI slave port to match the
2. Defines and generates a receive DMA descriptor in
3. Enables the SPI DMA engine for a receive access
4. Starts receiving the data on the appropriate SPI SCKx
A slave mode transmit operation is similar, except the DSP’s
core specifies the data buffer in memory space from which
to transmit data, generates and relinquishes control of the
transmit DMA descriptor, and begins filling the SPI port’s
data buffer. If the SPI controller isn’t ready on time to
transmit, it can transmit a “zero” word.
UART Port
The UART port provides a simplified UART interface to
another peripheral or Host. It performs full duplex, asyn-
chronous transfers of serial data. Options for the UART
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The SCKx line generates the programmed clock pulses
for simultaneously shifting data out on MOSIx and
shifting data in on MISOx. In DMA mode only, transfers
continue until the SPI DMA word count transitions
from 1 to 0.
In DMA mode only, reception continues until the SPI
DMA word count transitions from 1 to 0. The DSP’s core
could continue, by queuing up the next DMA descriptor.
size, and transfer format).
pin (reconfigured Programmable Flag pin).
memory space (optional in DMA mode only).
direction (optional in DMA mode only).
receive or transmit data buffer.
operation parameters set up on the master (data size
and transfer format) SPI transmitter.
Page 0 of memory space to interrupt at the end of the
data transfer (optional in DMA mode only).
(optional in DMA mode only).
edges after receiving an SPI chip select on an SPISSx
input pin (reconfigured Programmable Flag pin)
from a master
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
For current information contact Analog Devices at 800/262-5643
include support for 5–8 data bits; 1 or 2 stop bits; and none,
even, or odd parity. The UART port supports two modes
of operation:
• PIO (programmed I/O)
• DMA (direct memory access)
The UART’s baud rate (see
error code generation and status, and interrupts are
programmable:
• Supported bit rates range from 95 bits to 6.25M bits per
• Supported data formats are 7- or 12-bit frames.
• Transmit and receive status can be configured to generate
Figure 5. UART Clock Rate Calculation
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The timers can be used to provide a hardware-assisted
autobaud detection mechanism for the UART interface.
Programmable Flag (PFx) Pins
The ADSP-2195 has 16 bidirectional, general-purpose I/O,
Programmable Flag (PF15–0) pins. The PF7–0 pins are
dedicated to general-purpose I/O. The PF15–8 pins serve
either as general-purpose I/O pins (if the DSP is connected
to an 8-bit external data bus) or serve as DATA15–8 lines
(if the DSP is connected to a 16-bit external data bus). The
Programmable Flag pins have special functions for clock
multiplier selection and for SPI port operation. For more
information, see
Where D = 1 to 65536
The DSP’s core sends or receives data by writing or
reading I/O-mapped UATX or UARX registers, respec-
tively. The data is double-buffered on both transmit and
receive.
The DMA controller transfers both transmit and receive
data. This reduces the number and frequency of inter-
rupts required to transfer data to and from memory. The
UART has two dedicated DMA channels. These DMA
channels have lower priority than most DMA channels
because of their relatively low service rates.
second (100 MHz peripheral clock).
maskable interrupts to the DSP’s core.
UART Clock Rate
Serial Peripheral Interface (SPI) Ports on
=
Figure
HCLK
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September 2001
D
5), serial data format,
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