adsp-2186bca-160 Analog Devices, Inc., adsp-2186bca-160 Datasheet - Page 2

• Manufacturer Part Number: adsp-2186bca-160
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

SoundPort and EZ-ICE are registered trademarks of Analog Devices, Inc.
ADSP-2186
Fabricated in a high speed, double metal, low power, CMOS
process, the ADSP-2186 operates with a 25 ns instruction cycle
time. Every instruction can execute in a single processor cycle.
The ADSP-2186’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle the ADSP-2186 can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
This takes place while the processor continues to:
• Receive and transmit data through the two serial ports
• Receive and/or transmit data through the internal DMA port
• Receive and/or transmit data through the byte DMA port
• Decrement timer
Development System
The ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup-
ports the ADSP-2186. The System Builder provides a high level
method for defining the architecture of systems under develop-
ment. The Assembler has an algebraic syntax that is easy to
program and debug. The Linker combines object files into an
executable file. The Simulator provides an interactive instruction-
level simulation with a reconfigurable user interface to display
different portions of the hardware environment. A PROM
Splitter generates PROM programmer compatible files. The
C Compiler, based on the Free Software Foundation’s GNU
C Compiler, generates ADSP-2186 assembly source code.
The source code debugger allows programs to be corrected in
the C environment. The Runtime Library includes over 100
ANSI-standard mathematical and DSP-specific functions.
The EZ-KIT Lite is a hardware/software kit offering a complete
development environment for the entire ADSP-21xx family: an
ADSP-218x based evaluation board with PC monitor software
plus Assembler, Linker, Simulator and PROM Splitter software.
The ADSP-21xx EZ-KIT Lite is a low cost, easy to use hardware
platform on which you can quickly get started with your DSP soft-
ware design. The EZ-KIT Lite includes the following features:
• 33 MHz ADSP-2181
• Full 16-bit Stereo Audio I/O with AD1847 SoundPort
• RS-232 Interface to PC with Microsoft
• EZ-ICE
• DSP Demo Programs
The ADSP-218x EZ-ICE Emulator aids in the hardware debug-
ging of an ADSP-2186 system. The emulator consists of hard-
ware, host computer resident software, and the target board
connector. The ADSP-2186 integrates on-chip emulation sup-
port with a 14-pin ICE-Port interface. This interface provides a
simpler target board connection that requires fewer mechanical
clearance considerations than other ADSP-2100 Family EZ-
ICEs. The ADSP-2186 device need not be removed from the
target system when using the EZ-ICE, nor are any adapters
needed. Due to the small footprint of the EZ-ICE connector,
emulation can be supported in final board designs.
Codec
Control Software
®
Connector for Emulator Control
®
Windows 3.1
®
–2–
The EZ-ICE performs a full range of functions, including:
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
• Registers and memory values can be examined and altered
• PC upload and download functions
• Instruction-level emulation of program booting and execution
• Complete assembly and disassembly of instructions
• C source-level debugging
See Designing An EZ-ICE-Compatible Target System in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections), as
well as the Target Board Connector for EZ-ICE Probe section of
this data sheet, for the exact specifications of the EZ-ICE target
board connector.
Additional Information
This data sheet provides a general overview of ADSP-2186 func-
tionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User’s Manual, Third Edition. For more information about the
development tools, refer to the ADSP-2100 Family Development
Tools Data Sheet.
ARCHITECTURE OVERVIEW
The ADSP-2186 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation) in-
structions. Every instruction can be executed in a single proces-
sor cycle. The ADSP-2186 assembly language uses an algebraic
syntax for ease of coding and readability. A comprehensive set of
development tools supports program development.
Figure 1 is an overall block diagram of the ADSP-2186. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arith-
metic shifts, normalization, denormalization and derive exponent
operations.
The shifter can be used to efficiently implement numeric
format control including multiword and block floating-point
representations.
DATA ADDRESS
GENERATORS
DAG 1
ALU
ARITHMETIC UNITS
ADSP-2100 BASE
ARCHITECTURE
DAG 2
MAC
SHIFTER
SEQUENCER
PROGRAM
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
PROGRAM MEMORY ADDRESS
Figure 1. Block Diagram
PROGRAM
MEMORY
SPORT 0
8K
SERIAL PORTS
POWER-DOWN
24
MEMORY
CONTROL
SPORT 1
MEMORY
8K
DATA
16
PROGRAMMABLE
TIMER
FLAGS
AND
I/O
FULL MEMORY
CONTROLLER
EXTERNAL
EXTERNAL
EXTERNAL
INTERNAL
ADDRESS
HOST MODE
BYTE DMA
DATA
DATA
PORT
REV. A
DMA
BUS
BUS
BUS
MODE
OR