xa2c32a Xilinx Corp., xa2c32a Datasheet - Page 5

• Manufacturer Part Number: xa2c32a
• Description: Coolrunner-ii Automotive Cpld Product Family
• Manufacturer: Xilinx Corp.

Advanced Interconnect Matrix (AIM)
The Advanced Interconnect Matrix is a highly connected
low power rapid switch. The AIM is directed by the software
to deliver up to a set of 40 signals to each FB for the cre-
ation of logic. Results from all FB macrocells, as well as, all
pin inputs circulate back through the AIM for additional con-
nection available to all other FBs as dictated by the design
software. The AIM minimizes both propagation delay and
power as it makes attachments to the various FBs.
I/O Block
I/O blocks are primarily transceivers. However, each I/O is
either automatically compliant with standard voltage ranges
or can be programmed to become so. See
detailed information on CoolRunner-II I/Os.
Table 4
Table 4: CoolRunner-II Automotive CPLD I/O Standard Summary
Output Banking
CPLDs are widely used as voltage interface translators. To
that end, the output pins are grouped in large banks. The
32, 64,128, and 256-macrocell devices support two output
banks. Each bank can be set to a selected output voltage
level. If you want only one output voltage level, both banks
can be set to the same voltage. The large part (384-macro-
cell) supports four output banks split evenly. It can support
groupings of one, two, three or four separate output voltage
levels. This kind of flexibility permits easy interfacing to
3.3V, 2.5V, 1.8V, and 1.5V in a single part.
DS315 (v1.1) October 31, 2006
Product Specification
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
IOSTANDARD Attribute
summarizes the single ended I/O standard support.
R
To Macrocell
Direct Input
To AIM
Figure 4: CoolRunner-II Automotive CPLD I/O Block Diagram
Open Drain
GTS[0:3]
Disabled
Enabled
Hysteresis
CGND
CTE
PTB
4
XAPP382
From Macrocell
V
CCIO
3.3
3.3
2.5
1.8
1.5
www.xilinx.com
for
In addition to voltage levels, each input can selectively
arrive through Schmitt-trigger inputs. This adds a small time
delay, but substantially reduces noise on that input pin.
Approximately 500 mV of hysteresis will be added when
Schmitt-trigger inputs are selected. All LVCMOS inputs can
have hysteresis input. Hysteresis also allows easy genera-
tion of external clock circuits. The Schmitt-trigger path is
best seen in
patibility with I/O standards.
Outputs can be directly driven, 3-stated or open-drain con-
figured. A choice of slow or fast slew rate output signal is
also available.
age standards associated with specific part capacities. All
inputs and disabled outputs are voltage tolerant up to
V
DataGATE
Low power is the hallmark of CMOS technology. Other
CPLD families use a sense amplifier approach to creating
product terms, which always has a residual current compo-
nent being drawn. This residual current can be several hun-
dred milliamps, making them unusable in portable systems.
CoolRunner-II Automotive CPLDs use standard CMOS
methods to create the CPLD architecture and deliver the
corresponding low current consumption, without doing any
special tricks. However, sometimes designers would like to
CCIO
V CCIO
.
CoolRunner-II Automotive CPLD Product Family
Figure
Table 4
Schmitt-trigger Support
4. See
summarizes various supported volt-
Required
Optional
Optional
Optional
Optional
Table 4
Global termination
Pullup/Bus-Hold
for Schmitt-trigger com-
DS315_04_091906
5