xcr3064a Xilinx Corp., xcr3064a Datasheet - Page 11
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xcr3064a
Manufacturer Part Number
xcr3064a
Description
64 Macrocell Cpld With Enhanced Clocking , Inc
Manufacturer
Xilinx Corp.
Datasheet
1.XCR3064A.pdf
(18 pages)
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XCR3064A: 64 Macrocell CPLD With Enhanced Clocking
AC Electrical Characteristics
Commercial: 0 ° C ≤ T
11
t
t
t
t
t
t
t
t
t
t
f
f
f
t
t
t
t
t
t
t
t
t
Notes:
PD_PAL
PD_PLA
CO
SU_PAL
SU_PLA
H
CH
CL
R
F
MAX1
MAX2
MAX3
BUF
PDF_PAL
PDF_PLA
CF
INIT
ER
EA
RP
RR
Symbol
1. Specifications measured with one output switching. See
2. This parameter guaranteed by design and characterization, not by test.
3. Output C
Propagation delay time, input (or feedback node) to output through PAL
Propagation delay time, input (or feedback node) to output through
PAL + PLA
Clock to out (global synchronous clock from pin)
Setup time (from input or feedback node) through PAL
Setup time (from input or feedback node) through PAL + PLA
Hold time
Clock High time
Clock Low time
Input Rise time
Input Fall time
Maximum FF toggle rate
Maximum internal frequency
Maximum external frequency
Output buffer delay time
Input (or feedback node) to internal feedback node delay time through
PAL
Input (or feedback node) to internal feedback node delay time through
PAL+PLA
Clock to internal feedback node delay time
Delay from valid V
Input to output disable
Input to output valid
Input to register preset
Input to register reset
2
L
= 5 pF.
AMB
2
2
≤ +70 ° C; 3.0V ≤ V
2
2
2
2
CC
2
2
to valid reset
2, 3
2
2
2
(1/t
2
2
CH
(1/t
Parameter
(1/t
CC
+ t
SUPAL
SUPAL
1
2
≤ 3.6V
CL
For Commercial Grade Devices
)
+ t
+ t
www.xilinx.com
1-800-255-7778
CF
2
CO
)
)
Figure 6
and
Table 6
for derating.
Min.
250
143
111
3.5
2
3
2
5
2
2
DS037 (v1.1) February 10, 2000
7
Max.
100
100
7.5
5.5
5.5
3.5
20
9
0
2
7
8
8
9
9
Min.
200
105
6.5
2.5
2.5
83
2
3
2
5
10
Max.
11.5
100
100
9.5
4.5
9.5
9.5
9.5
9.5
10
20
7
0
2
8
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µ s
ns
ns
ns
ns
R