atf280e ATMEL Corporation, atf280e Datasheet - Page 11

• Manufacturer Part Number: atf280e
• Description: Rad Hard Reprogrammable Fpga
• Manufacturer: ATMEL Corporation

ATF280E
INIT is a multi-function pin. During power-on-reset and manual reset, the pin functions as an
open drain bi-directional I/O which releases High when the configuration clear cycle is complete,
but can be held Low to hold the configuration in a reset state. Once released, the FPGA will pro-
ceed to either configuration download or idle, as appropriate. During configuration download, the
INIT pin is again an open drain bi-directional pin which signals if an error is encountered during
the download of a configuration bitstream. In addition, during the Check Function, the INIT pin
drives Low for any configuration SRAM mismatch (see the description of the Check Function on
page 16 for more details). While in open drain mode, the pin is pulled to VDD with a nominal 20K
internal resistor. When not configuring, the INIT pin becomes a fully functional user I/O.
CON - Configuration Status (Input/Output)
CON is the FPGA configuration start and status pin. It is a dedicated open drain bi-directional
pin. During power-on-reset or manual reset, CON is driven Low by the FPGA. In Modes 2, 6, or
7, when the FPGA has finished the configuration clear cycle, CON is released to indicate the
device is ready for the user to initiate configuration download. The user may then drive CON
Low to initiate a configuration download. After three clock cycles, CON is then driven Low by the
FPGA until it finishes the download, and it is then released. In Mode 0, CON is not released by
the FPGA at the end of power-on-reset or manual reset. Instead, CON is controlled by the FPGA
until the end of the auto-configuration process. CON is released at the end of configuration
download in Mode 0, and the user may then initiate a manual configuration download by driving
CON Low. While in open drain mode, the pin is pulled to VDD with a nominal 10K internal
resistor.
HDC - High During Configuration (output)
HDC(1) is driven High by the FPGA during power-on-reset, manual reset, and configuration
download. During normal operation, the pin is a fully functional user I/O.
Note: 1. All user I/O default to inputs with pull-ups “on”. The HDC pin transitions from driving a
strong “1” to a pull-up “1” after reset. The HDC pin will transition from driving a strong “1” to the
user programmed state at the end of configuration download. If not programmed, the default
state is input with pull-up.
LDC - Low During Configuration (output)
HDC(1) is driven Low by the FPGA during power-on-reset, manual reset, and configuration
download. During normal operation, the pin is a fully functional user I/O.
Note: 1. All user I/O default to inputs with pull-ups “on”. The HDC pin transitions from driving a
strong “1” to a pull-up “1” after reset. The HDC pin will transition from driving a strong “1” to the
user programmed state at the end of configuration download. If not programmed, the default
state is input with pull-up.
D0 - Configuration Data Bus - LSB (Input/Output)
D0 is the lsb of the FPGA configuration data bus used to download configuration data to the
device. During power-on-reset or manual reset, D0 is controlled by the configuration SRAM. The
D0 pin will transition from the user programmed state to a CMOS input with a nominal 20K inter-
nal pull-up resistor as the SRAM at that location is cleared by the configuration clear cycle. D0
becomes an input during configuration download.
D1:D15 - Configuration Data Bus - Upper bits (Input/Output)
D1:D15 are the upper bits of the 8/16-bit parallel data bus used to download configuration data
to the device. During power-on-reset or manual reset, D1:D15 are controlled by the configura-
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