atf22lv10c-15xi ATMEL Corporation, atf22lv10c-15xi Datasheet - Page 6

• Manufacturer Part Number: atf22lv10c-15xi
• Description: High- Performance Ee Pld
• Manufacturer: ATMEL Corporation

4.7
4.8
5. Electronic Signature Word
6. Security Fuse Usage
7. Programming/Erasing
8. Input and I/O Pin-keeper
6
Power-up Reset
Preload of Register Outputs
ATF22LV10C
The registers in the ATF22LV10C are designed to reset during power-up. At a point delayed
slightly from V
depend on the polarity of the buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature
of reset and the uncertainty of how V
required:
The ATF22LV10C registers are provided with circuitry to allow loading of each register with
either a high or a low. This feature will simplify testing since any state can be forced into the reg-
isters to control test sequencing. A JEDEC file with preload is generated when a source file with
vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done automati-
cally by most of the approved programmers after the programming.
There are 64 bits of programmable memory that are always available to the user, even if the
device is secured. These bits can be used for user-specific data.
A single fuse is provided to prevent unauthorized copying of the ATF22LV10C fuse patterns.
Once programmed, fuse verify and preload are inhibited. However, the 64-bit User Signature
remains accessible.
The security fuse should be programmed last, as its effect is immediate.
Programming/erasing is performed using standard PLD programmers. See CMOS PLD Pro-
gramming Hardware & Software Support for information on software/programming.
Table 7-1.
All ATF22V10C family members have internal input and I/O pin-keeper circuits. Therefore,
whenever inputs or I/Os are not being driven externally, they will maintain their last driven state.
This ensures that all logic array inputs and device outputs are at known states. These are rela-
tively weak active circuits that can be easily overridden by TTL-compatible drivers (see Input
and I/O diagrams on page 8).
Parameter
T
V
1. The V
2. The clock must remain stable during T
3. After T
PR
RST
high.
CC
PR
CC
rise must be monotonic and start below 0.7V.
, all input and feedback setup times must be met before driving the clock pin
Programming/Erasing
crossing V
Description
Power-up Reset Time
Power-up Reset Voltage
RST
, all registers will be reset to the low state. The output state will
CC
actually rises in the system, the following conditions are
PR
.
Typ
600
2.5
1,000
Max
3.0
0780L–PLD–12/05
Units
ns
V