hi5905n Intersil Corporation, hi5905n Datasheet - Page 7

• Manufacturer Part Number: hi5905n
• Description: 14-bit, 5 Msps, Military A/d Converter
• Manufacturer: Intersil Corporation

Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
Power Supply Rejection Ratio (PSRR)
Each of the power supplies are moved plus and minus 5%
and the shift in the offset and gain error (in LSBs) is noted.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to evaluate
the dynamic performance of the HI5905. A low distortion sine
wave is applied to the input, it is coherently sampled, and the
output is stored in RAM. The data is then transformed into the
frequency domain with an FFT and analyzed to evaluate the
dynamic performance of the A/D. The sine wave input to the
part is -0.5dB down from full-scale for all these tests. SNR and
SINAD are quoted in dB. The distortion numbers are quoted in
dBc (decibels with respect to carrier) and DO NOT include any
correction factors for normalizing to full scale.
Signal-to-Noise Ratio (SNR)
SNR is the measured RMS signal to RMS noise at a
specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components except the
fundamental and the first five harmonics.
Signal-to-Noise + Distortion Ratio (SINAD)
SINAD is the measured RMS signal to RMS sum of all
other spectral components below the Nyquist frequency,
f
Effective Number Of Bits (ENOB)
The effective number of bits (ENOB) is calculated from the
SINAD data by:
where: V
V
fullscale.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input signal.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the applicable harmonic
component to the RMS value of the fundamental input signal.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spur or spectral
component (excluding the first 5 harmonic components) in
the spectrum below f
Intermodulation Distortion (IMD)
Nonlinearities in the signal path will tend to generate
intermodulation products when two tones, f
ENOB = SINAD + V
S
CORR
/2, excluding DC.
adjusts the ENOB for the amount the input is below
CORR
= 0.5dB (Typical)
CORR
S
/2.
-1.76 /6.02
4-7
1
and f
2
, are
present at the inputs. The ratio of the measured signal to the
distortion terms is calculated. The terms included in the
calculation are (f
(f
below full scale.
Transient Response
Transient response is measured by providing a fullscale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
14-bit accuracy.
Over-Voltage Recovery
Over-voltage Recovery is measured by providing a fullscale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 14-bit accuracy.
Full Power Input Bandwidth (FPBW)
Full power input bandwidth is the analog input frequency at
which the amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sinewave.
The input sinewave has an amplitude which swings from -f
to +f
sampling frequency.
Timing Definitions
Refer to Figure 1, Internal Circuit Timing, and Figure 2,
Input-To-Output Timing, for these definitions.
Aperture Delay (t
Aperture delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (t
Aperture Jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Data Hold Time (t
Data hold time is the time to where the previous data (N - 1)
is still valid.
Data Output Delay Time (t
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (t
After the analog sample is taken, the digital data is output on
the bus at the third cycle of the clock. This is due to the
pipeline nature of the converter where the data has to ripple
through the stages. This delay is specified as the data
latency. After the data latency time, the data representing
each succeeding sample is output at the following clock
pulse. The digital data lags the analog input sample by 4
clock cycles.
1
+ 2f
S
. The bandwidth given is measured at the specified
2
), (f
1
- 2f
2
1
). The ADC is tested with each tone 6dB
+ f
LAT
AJ
2
AP
H
), (f
)
)
)
)
1
- f
2
), (2f
OD
1
)
), (2f
2
), (2f
1
+ f
2
), (2f
1
- f
2
S
),