dac088s085eb National Semiconductor Corporation, dac088s085eb Datasheet - Page 14

• Manufacturer Part Number: dac088s085eb
• Description: 8-bit Micro Power Octal Digital-to-analog Converter With Rail-to-rail Outputs
• Manufacturer: National Semiconductor Corporation

www.national.com
idled high to avoid the activation of daisy chain operation
where D
1.5 DAISY CHAIN OPERATION
Daisy chain operation allows communication with any number
of DAC088S085s using a single serial interface. As long as
the correct number of data bits are input in a write sequence
(multiple of sixteen bits), a rising edge of SYNC will properly
update all DACs in the system.
To support multiple devices in a daisy chain configuration,
SCLK and SYNC are shared across all DAC088S085s and
D
second. Figure 6 shows three DAC088S085s connected in
daisy chain fashion. Similar to a single channel write se-
quence, the conversion for a daisy chain operation begins on
a falling edge of SYNC and ends on a rising edge of SYNC.
A valid write sequence for n devices in a chain requires n
times 16 falling edges to shift the entire input data stream
through the chain. Daisy chain operation is guaranteed for a
maximum SCLK speed of 30MHz.
1.6 SERIAL INPUT REGISTER
The DAC088S085 has two modes of operation plus a few
special command operations. The two modes of operation are
Write Register Mode (WRM) and Write Through Mode
(WTM). For the rest of this document, these modes will be
referred to as WRM and WTM. The special command oper-
OUT
of the first DAC in the chain is connected to D
OUT
FIGURE 6. Daisy Chain Configuration
DB[15:12]
is active.
1 0 0 0
1 0 0 1
X X X X X X X X X X X X
X X X X X X X X X X X X
DB[11:0]
TABLE 1. Write Register and Write Through Modes
FIGURE 7. Daisy Chain Timing Diagram
IN
30031367
of the
WRM: The registers of each DAC Channel can be written to
without causing their outputs to change.
WTM: Writing data to a channel's register causes the DAC
output to change.
14
The serial data output pin, D
DAC088S085
DAC088S085 devices in a system. In a write sequence,
D
before going high on the fifteenth falling edge. Subsequently,
the next sixteen falling edges of SCLK will output the first six-
teen data bits entered into D
three DAC088S085s in Figure 6. In this instance, It takes
forty-eight falling edges of SCLK followed by a rising edge of
SYNC to load all three DAC088S085s with the appropriate
register data. On the rising edge of SYNC, the programmed
function is executed in each DAC088S085 simultaneously.
ations are separate from WRM and WTM because they can
be called upon regardless of the current mode of operation.
The mode of operation is controlled by the first four bits of the
control register, DB15 through DB12. See Table 1 for a de-
tailed summary.
OUT
remains low for the first fourteen falling edges of SCLK
Description of Mode
to
allow
IN
daisy-chaining
. Figure 7 shows the timing of
OUT
, is available on the
of
30031368
multiple