x9438 Intersil Corporation, x9438 Datasheet - Page 4

• Manufacturer Part Number: x9438
• Description: Dual Digitally Controlled Potentiometer Xdcp With Operational Amplifier
• Manufacturer: Intersil Corporation

The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9438 to respond with an acknowledge. The
A
signals or tied to V
Acknowledge Polling
The disabling of the inputs, during the internal non-vol-
atile write operation, can be used to take advantage of
the typical 5ms EEPROM write cycle time. Once the
stop condition is issued to indicate the end of the non-
volatile write command the X9438 initiates the internal
write cycle. ACK polling (Flow 1) can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9438 is
still busy with the write operation no ACK will be
returned. If the X9438 has completed the write opera-
tion an ACK will be returned and the master can then
proceed with the next operation.
Flow 1. ACK Polling Sequence
0
- A
3
Command Completed
inputs can be actively driven by CMOS input
Enter Ack Polling
Nonvolatile Write
Issue Slave
Operation?
Returned?
Instruction
Prooceed
Address
START
Further
Issue
Issue
ACK
Yes
Yes
0
CC
- A
or V
3
No
inputs. The X9438 compares
SS
No
4
.
Issue STOP
Prooceed
Issue STOP
X9438
Instruction Structure
The byte following the address contains the instruction
and register pointer information. The four most signifi-
cant bits are the instruction. The next four bits point to
one of the two pots and when applicable they point to
one of the four WCRs associated data registers. The
format is shown below in Figure 2.
Figure 2. Instruction Byte Format
The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the two regis-
ters that is to be acted upon when a register oriented
instruction is issued. The last bit (P0) selects which
one of the two potentiometers is to be affected by the
instruction.
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is illus-
trated in Figure 3. These two-byte instructions
exchange data between the wiper counter register and
one of the data registers. A transfer from a data regis-
ter to a wiper counter register is essentially a write to a
static RAM. The response of the wiper to this action
will be delayed t
register (current wiper position) to a data register is a
write to non-volatile memory and takes a minimum of
t
of the two potentiometers and one of its associated
registers; or it may occur globally, wherein the transfer
occurs between all of the potentiometers and one of
their associated registers.
Four instructions require a three-byte sequence to
complete. The basic sequence is illustrated in Figure
4. These instructions transfer data between the host
and the X9438; either between the host and one of the
data registers or directly between the host and the
wiper counter and analog control registers. These
instructions are: 1) Read Wiper Counter Register or
read the current wiper position of the selected pot, 2)
Write Wiper Counter Register, i.e. change current
wiper position of the selected pot; 3) Read Data Regis-
ter, read the contents of the selected non-volatile regis-
ter; 4) Write Data Register, write a new value to the
selected data register. The bit structures of the instruc-
tions are shown in Figure 6.
WR
to complete. The transfer can occur between one
I3
Instructions
I2
WRL
I1
. A transfer from the wiper counter
I0
Register
R1
Select
R0
WCR Select
0
P0
March 11, 2005
FN8199.0