qt300 Quantum Research Group, qt300 Datasheet - Page 4

• Manufacturer Part Number: qt300
• Description: Capacitance To Digital Converter
• Manufacturer: Quantum Research Group

When not communicating, all SPI lines float to allow multiple
chips to connect over the same SPI lines. A pullup or
pulldown resistor is required on SCK depending on the
selected clock phase, determined by Setups. A pullup
resistor is required on /DRDY. /REQ may require a pullup if
the host ever allows this line to float.
3.3 SPI Bus Sharing
All SPI float transfers making it possible to have several
QT300 devices (or other unrelated devices) share the SPI
control signals (Figure 3-1).
Each part needs an individual /REQ line, but /DRDY, SCK
and SDO can be connected together.
3.4 SPI Slave Mode
Refer to Figure 7-1 and Table 7-1, page 7.
In SPI Slave mode, /DRDY is used to let the host know when
data is ready for collection in response to a request so that
the host can clock over the data.
SPI Slave mode uses 4 signals:
/REQ - Request Acquisition Input; Active low input-only.
LQ
When /REQ is pulled low, the QT300 wakes and starts an
acquire. The IC will transmit the resulting data only when
the acquire has finished.
Figure 3-1 Multiple QT300's on the same SPI port
HOST MICRO
DRDY
REQ
SCK
SDI
Vdd
Vdd
QT300
QT300
QT300
1
2
6
7
1
2
6
7
1
2
6
7
DRDY
SCK
REQ
SDO
DRDY
SCK
REQ
SDO
DRDY
SCK
REQ
SDO
Vdd
8
Vdd
Vss
4
Vdd
8
Vdd
Vss
4
Vdd
8
Vdd
Vss
4
SNS1
SNS2
SNS1
SNS2
SNS1
SNS2
3
5
3
5
3
5
100nF
100nF
100nF
ELECTRODE
ELECTRODE
ELECTRODE
Cs
Cs
Cs
Rs
Rs
Rs
Cx
Cx
Cx
4
SDO - Serial Data Output; Output-only. This is the data
SCK - SPI clock; Idle high or idle low; input-only SPI clock
/DRDY - Data Ready; active low output only. This indicates to
A typical SPI slave mode communication sequence is:
3.5 SPI Master Mode
Refer to Figure 7-2 and Table 7-2, page 7.
In master SPI mode the QT300 generates the clock signal
after an acquire initiated from the host via the /REQ line. The
clock speed and the spacing between the two bytes is set via
the Setup process (Section 6).
SCD setup parameter determines the master-mode clock
rate. The default value is 55 (resulting in a 2.55KHz rate).
The relationship is:
MLS setup parameter determines the spacing between the
two return bytes; this can be important to allow a slow host
device to recover from receiving the first byte to prevent an
1) Host pulses /REQ low for ≥30µs to initiate an acquire.
2) QT300 acquires a signal in response to /REQ.
3) QT300 pulls /DRDY low when ready to send data back.
4) Host detects /DRDY is low.
5) Host clocks out the high byte of data from the QT300.
6) Host waits for ≥12µs.
7) Host clocks out the low byte of data from the QT300.
8) QT300 releases /DRDY to float high.
/REQ should return high before the end of the burst. If
/REQ is still low at the end of the burst the part will go into
Setup mode. The minimum duration of /REQ is 30µs.
output to the host during an SPI transfer. When not in use,
this pin floats. This pin should be connected to the SDI
input pin of the host device.
from the host. The idle state is determined in Setups by
the serial mode (SM) parameter.
If SM is set for idle-low SCK: Data is shifted out of the
QT300 on the rising edge of SCK and should be shifted
into the host on the falling edge of SCK.
If SM is set for idle-high SCK: Data is shifted out of the
QT300 on the falling edge of SCK and should be shifted
into the host on the rising edge of SCK.
The maximum clock speed is 40kHz, and the timings
should obey the parameters Tskh and Tskl in Table 7-1.
the host that the device is ready to send data back to the
host. During idle times this pin floats and therefore must
be connected to a pullup resistor. The host must wait until
/DRDY goes low before starting an SPI transfer.
Between the high and low byte clockings, the host should
observe a delay of ≥12µs.
Fscd = 1200/(30+ (SCD x 8)) in Khz
Where SCD = 0..255
QT300 R1.02/0204