sx8675iwltrt Semtech Corporation, sx8675iwltrt Datasheet - Page 45

• Manufacturer Part Number: sx8675iwltrt
• Description: Haptics Enabled Multitouch 4/5-wire Resistive Touchscreen Controller With Proximity Sensing
• Manufacturer: Semtech Corporation

SX8674/SX8675/SX8676
Haptics Enabled Multitouch 4/5-Wire
Resistive Touchscreen Controller with Proximity Sensing
ADVANCED COMMUNICATIONS & SENSING
The correct sampling of the screen by the chip and the host I2C bus traffic are events that might occur
simultaneously. The chip will synchronize these events by the use of clock stretching if that is required. The
stretching occurs directly after the last received command bit (see figure above).
11.4 Read Register
The I2C read register sequence is given in figure below. After the start condition [S], the chip slave address (SA)
is sent, followed by an eighth bit (W=‘0’) indicating a write. The chip then acknowledges [A] that it is being
addressed, and the host responds with a CR byte consisting in ‘01’ followed by the register address (RA). The
chip acknowledges [A] and the host sends the repeated start Condition [Sr]. Once again, the chip slave address
(SA) is sent, followed by an eighth bit (R=‘1’) indicating a read. The chip responds with an acknowledge [A] and
the data byte (RD0). If the host needs to read more data it will acknowledge [A] and the chip will send the next
data byte (RD1). This sequence will be repeated until the host terminates the transfer with a NACK [N] followed
by a stop condition [P].
Figure 54 – I2C Read Register
The register address increments automatically when successive data bytes (RD1...RDn) are read by the host.
The correct sampling of the screen by the chip and the host I2C bus traffic are events that might occur
simultaneously. The chip will synchronize these events by the use of clock stretching if that is required. The
stretching occurs directly after the last received command bit (see figure above).
11.5 Write Command (Touchscreen Interface)
The I2C write command sequence is given in figure below. After the start condition [S], the chip slave address
(SA) is sent, followed by an eighth bit (W=‘0’) indicating a write. The chip then acknowledges [A] that it is being
addressed, and the host responds with a CR byte consisting in Command(7:0) (see table below). The chip
acknowledges [A] and the host sends a stop [P].
Figure 55 – I2C Write Command
The sampling of the screen by the chip and the host I2C bus traffic are events that might occur simultaneously.
The chip will synchronize these events by the use of clock stretching if that is required. The stretching occurs
directly after the last received command bit (see figure above).
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Rev 1 – 25
July 2011
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