cs5102a Cirrus Logic, Inc., cs5102a Datasheet - Page 34

• Manufacturer Part Number: cs5102a
• Description: 16-bit, 100/20 Khz A/d Converters
• Manufacturer: Cirrus Logic, Inc.

8.2
8.3
34
CLKIN - Clock Input, PIN 3.
XOUT - Crystal Output, PIN 4.
HOLD - Hold, PIN 12.
CRS/FIN - Coarse Charge/Fine Charge Control, PIN 10.
CH1/2 - Left/Right Input Channel Select, PIN 13.
SLEEP - Sleep, PIN 28.
CODE - 2's Complement/Binary Coding Select, PIN 16.
BP/UP - Bipolar/Unipolar Input Range Select, PIN 17.
SCKMOD - Serial Clock Mode Select, PIN 27.
OUTMOD - Output Mode Select, PIN 18.
Oscillator
All conversions and calibrations are timed from a master clock which can be externally supplied by
driving CLKIN [this input TTL-compatible, CMOS recommended].
The master clock can be generated by tying a crystal across the CLKIN and XOUT pins. If an external
clock is used, XOUT must be left floating.
Digital Inputs
A falling transition on this pin sets the CS5101A or CS5102A to the hold state and initiates a
conversion. This input must remain low for at least 1/tclk + 20 ns. When operating in Free Run Mode,
HOLD is disabled, and should be tied to DGND or VD+.
When brought high during acquisition time, CRS/FIN forces the CS5101A or CS5102A into coarse
charge state. This engages the internal buffer amplifier to track the analog input and charges the
capacitor array much faster, thereby allowing the CS5101A or CS5102A to track high-slewing signals. In
order to get an accurate sample, the last coarse charge period before initiating a conversion (bringing
HOLD low) must be longer than 0.75µs (CS5101A) or 3.75µs (CS5102A). Similarly, the fine charge
period immediately prior to conversion must be at least 1.125µs (CS5101A) or 5.625µs (CS5102A). The
CRS/FIN pin must be low during conversion time. For normal operation, CRS/FIN should be tied low, in
which case the CS5101A or CS5102A will automatically enter coarse charge for 6 clock cycles
immediately after the end of conversion.
Status at the end of a conversion cycle determines which analog input channel will be acquired for the
next conversion cycle. When in Free Run Mode, CH1/2 is an output, and will indicate which channel is
being sampled during the current acquisition phase.
When brought low causes the CS5101A or CS5102A to enter a power-down state. All calibration
coefficients are retained in memory, so no recalibration is needed after returning to the normal operating
mode. If using the internal crystal oscillator, time must be allowed after SLEEP returns high for the
crystal oscillator to stabilize. SLEEP should be tied high for normal operation.
Determines whether output data appears in 2's complement or binary format. If high, 2's complement; if
low, binary.
When low, the CS5101A or CS5102A accepts a unipolar input range from AGND to VREF. When high,
the CS5101A or CS5102A accepts bipolar inputs from -VREF to +VREF.
When high, the SCLK pin is an input; when low, it is an output. Used in conjunction with OUTMOD to
select one of 4 output modes described in Table 2.
The status of SCKMOD and OUTMOD determine which of four output modes is utilized. The four
modes are described in Table 2.
CS5101A CS5102A
DS45F6