clc520 National Semiconductor Corporation, clc520 Datasheet - Page 11

• Manufacturer Part Number: clc520
• Description: Amplifier With Voltage Controlled Gain, Agc+amp
• Manufacturer: National Semiconductor Corporation

Application Information
the model should predict the equivalent output noise above
the flicker noise region to within a few dB of actual perfor-
mance over the normal range of A
values.
Calculating CLC520 output noise in a typical circuit
To calculate the noise in a CLC520 application, the noise
terms given for the amplifier as well as the noise terms of the
external components must be included. To clarify the tech-
niques used, output noise in a typical circuit will be calcu-
lated. ( Figure 6 )
The noise model is depicted in Figure 7 . The diagram as-
sumes spot noise source with V
units. The Thevenin equivalent of the source and input ter-
mination is used; 25
R
The internal 5k
assumed noiseless since its effect is included in i
noise contribution from R
The easiest way to analyze the output noise of this circuit is
to divide the noise power into three pieces; −input buffer
noise calculation, output buffer noise and core noise. The
input buffer varies with the gain. The output buffer term is
constant. The core noise term is zero at both maximum and
minimum gain and reaches peak at A
Since we assume all noise terms are uncorrelated, the
equivalent input noise voltage squared is given by:
i
input buffer inverting input is grounded. e
Figure 5 .
The equivalent output buffer noise is given by:
i
g
does not contribute to the output buffer noise because the
is assumed noiseless since its effect is included in e
FIGURE 7. Noise Model for Typical Circuit
FIGURE 6. Typical Circuit
resistor at the CLC520 core output is also
in series with a noise voltage source.
f
is modeled as a noise source.
rms
/
VMAX
VMAX
and Amps
(Continued)
/2.
and component
n
is taken from
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/
, The
n
.
11
i
output buffer non-inverting input is grounded.
The core noise is already output referred and is 37nV/
at V
A
total output noise power.
The total output noise voltage is given by:
Where A
with V
C accounts for the variation in core noise contribution as V
is adjusted. C=1 when gain A
A
values.
Using these equations, total calculated output noise for the
circuit was 20nV/
mid-gain, and 53nV/
AGC circuits
Figure 8 shows a typical AGC circuit. The CLC520 is fol-
lowed up with a CLC401 for higher overall gain. The output
of the CLC401 is rectified and fed to an inverting integrator
using a CLC420 (wideband voltage feedback op amp).
When the output voltage, V
output voltage ramps down reducing the net gain of the
CLC520 and V
integrator ramps up increasing the net gain and the output
voltage. Actual output level is set with R1. To prevent shifts in
DC output voltage with DC changes in input signal level, trim
pot R2 is provided. AGC circuits are always limited in the
range of input signals over which constant output level can
be maintained. In this circuit, we would expect that reason-
able AGC action could be maintained over the gain adjust-
ment range of the CLC520 (at least 40dB). In practice,
rectifier dynamic range limits reduce this slightly.
Evaluation Board
Evaluation PC boards (part number 730029 for through-hole
and 730023 for SOIC) for the CLC520 are available.
no
VMAX
VMAX
does not contribute to the output buffer noise because the
g
FIGURE 8. Automatic Gain Control (AGC) Loop
=1.1 (A
g
.
and A
Summing the noise power for each term gives the
V
is the input to output voltage gain, which varies
VMAX
V
= 0 and varies between 0 and 1 for all other
OUT
/2) and approaches zero as A goes to 0 or
. If the output voltage is too small, the
at minimum gain, 49nV/
at maximum gain.
OUT
V
, is too large the integrator
is A
VMAX
/2. C is zero at
www.national.com
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g