hi7191 Intersil Corporation, hi7191 Datasheet - Page 13

• Manufacturer Part Number: hi7191
• Description: 24-bit, High Precision, Sigma Delta A/d Converter
• Manufacturer: Intersil Corporation

notch code NOT the absolute frequency. The error is
seen when the user applies mid-scale (0V input, Bipolar
mode). With this input, the expected digital output
should be mid-scale (800000
probability, of an erroneous negative full scale (000000
output. Refer to Technical Brief TB348 for complete
details.
The FP10 to FP0 bits programmed into the Control Register
determine the cutoff (or notch) frequency of the digital filter.
The allowable code range is 00A
maximum and minimum cutoff frequency of 1.953kHz and
10Hz, respectively when operating at a clock frequency of
10MHz. If a 1MHz clock is used then the maximum and
minimum cutoff frequencies become 195.3kHz and 1Hz,
respectively. A plot of the (sinx/x)
is shown in Figure 10. This filter provides greater than 120dB
of 50Hz or 60Hz rejection. Changing the clock frequency or
the programming of the FP bits does not change the shape
of the filter characteristics, it merely shifts the notch
frequency. This low pass digital filter at the output of the
converter has an accompanying settling time for step inputs
just as a low pass analog filter does. New data takes
between 3 and 4 conversion periods to settle and update on
the serial port with a conversion period t
1/f
Input Filtering
The digital filter does not provide rejection at integer
multiples of the modulator sampling frequency. This implies
that there are frequency bands where noise passes to the
output without attenuation. For most cases this is not a
problem because the high oversampling rate and noise
shaping characteristics of the modulator cause this noise to
become a small portion of the broadband noise which is
filtered. However, if an anti-alias filter is necessary a single
pole RC filter is usually sufficient.
If an input filter is used the user must be careful that the
source impedance of the filter is low enough not to cause
FIGURE 9. LOW PASS FILTER FREQUENCY CHARACTERISTICS
N
.
-100
-120
-20
-40
-60
-80
0
f
C
ALIAS BAND
f
N
f
±f
N
C
FREQUENCY (Hz)
13
h
). Instead, there is a small
2f
3
H
N
digital filter characteristics
. This corresponds to a
CONV
3f
N
being equal to
4f
N
h
)
HI7191
gain errors in the system. The DC input impedance at the
inputs is >1GΩ but it is a dynamic load that changes with
clock frequency and selected gain. The input sample rate,
also dependent upon clock frequency and gain, determines
the allotted time for the input capacitor to charge. The
addition of external components may cause the charge time
of the capacitor to increase beyond the allotted time. The
result of the input not settling to the proper value is a system
gain error which can be eliminated by system calibration of
the HI7191.
Clocking/Oscillators
The master clock into the HI7191 can be supplied by either a
crystal connected between the OSC
shown in Figure 10A or a CMOS compatible clock signal
connected to the OSC
input sampling frequency, modulator sampling frequency,
filter -3dB frequency, output update rate, and calibration time
are all directly related to the master clock frequency, f
For example, if a 1MHz clock is used instead of a 10MHz
clock, what is normally a 10Hz conversion rate becomes a
1Hz conversion rate. Lowering the clock frequency will also
lower the amount of current drawn from the power supplies.
Please note that the HI7191 specifications are written for a
10MHz clock only.
Operational Modes
The HI7191 contains several operational modes including
calibration modes for cancelling offset and gain errors of
both internal and external circuitry. A calibration routine
should be initiated whenever there is a change in the
ambient operating temperature or supply voltage. Calibration
should also be initiated if there is a change in the gain, filter
notch, bipolar, or unipolar input range. Non-calibrated data
can be obtained from the device by writing 000000 to the
Offset Calibration Register, 800000 (h) to the Positive Full
FIGURE 10. OSCILLATOR CONFIGURATIONS
10MHz
OSC
1
17
pin as shown in Figure 10B. The
FIGURE 10A.
OSC
FIGURE 10B.
1
17
HI7191
10MHz
1
HI7191
OSC
CONNECTION
1
and OSC
16
OSC
2
NO
16
2
2
pins as
June 1, 2006
OSC
FN4138.8
.