kad5512p-21 ETC-unknow, kad5512p-21 Datasheet

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... VCM Key Specifications x SNR = 64.3dBFS for f x SFDR = 80dBc for f x Power consumption = 400mW Pin-Compatible Family Model KAD5514P-25 KAD5514P-21 KAD5514P-17 KAD5514P-12 KAD5512P-50 KAD5512P-25, KAD5512HP-25 KAD5512P-21, KAD5512HP-21 KAD5512P-17, KAD5512HP-17 KAD5512P-12, KAD5512HP-12 KAD5510P-50 Sales: 1-781-497-0060 CLKOUTP CLKOUTN D[11:0]P D[11:0]N ORP VREF ORN OUTFMT OUTMODE VREF 1.25 V ...

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... KAD5512P-50 Table of Contents Section Electrical Specifications DC Specifications AC Specifications Digital Specifications Timing Diagrams Switching Specifications Absolute Maximum Ratings Thermal Impedance ESD Pinout/Package Information Pin Descriptions Pin Configuration Typical Performance Characteristics Theory of Operation Functional Description Power-On Calibration User-Initiated Reset Analog Input Clock Input ...

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... Common-Mode Output Voltage Power Requirements 1.8V Analog Supply Voltage 1.8V Digital Supply Voltage 1.8V Analog Supply Current 1.8V Digital Supply Current Power Supply Rejection Ratio Power Dissipation Normal Mode Nap Mode Sleep Mode Rev 0.5.1 Preliminary = 500MSPS. SAMPLE KAD5512P-50 Symbol Conditions Min V Differential 1. Differential IN C Differential IN A ...

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... Spurious-Free Dynamic Range 1 Intermodulation Distortion Two-Tone SFDR Word Error Rate Full Power Bandwidth 1. SFDR, SINAD and ENOB specifications apply after gain error and timing skew between ADC cores have been minimized through external calibration. Rev 0.5.1 Preliminary KAD5512P-50 Conditions Min Typ DNL f = 10MHz -1.0 ±0.5 ...

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... KAD5512P-50 Digital Specifications Parameter Inputs Input Current High (RESETN) Input Current Low (RESETN) Input Current High (OUTMODE, NAP/SLP, CLKDIV, OUTFMT ) Input Current Low (OUTMODE, NAP/SLP, CLKDIV, OUTFMT ) Input Capacitance LVDS Outputs Differential Output Voltage Output Offset Voltage Output Rise Time Output Fall Time ...

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... KAD5512P-50 Switching Specifications Parameter ADC Aperture Delay RMS Aperture Jitter Input Clock to Output Clock Propagation Delay Input Clock to Data Propagation Delay Output Clock to Data Propagation Delay Latency (Pipeline Delay) Over Voltage Recovery Absolute Maximum Ratings Parameter AVDD to AVSS OVDD to OVSS AVSS to OVSS ...

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... KAD5512P-50 Thermal Impedance Parameter Junction to Paddle 2 Junction to Case 2 Junction to Ambient 2 2. Paddle soldered to ground plane. ESD Electrostatic charge accumulates on humans, tools and equipment and may discharge through any metallic package contacts (pins, balls, exposed paddle, etc integrated circuit. Industry-standard protection techniques have been utilized in the design of this prod- uct ...

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... KAD5512P-50 Pin Descriptions Pin # LVDS [LVCMOS] Name 1, 6, 12, 19, 24, 71 AVDD 2-5, 13, 14, 17, 18, 28-31 DNC 7, 8, 11, 72 AVSS 9, 10 VINN, VINP 15 VCM 16 CLKDIV 20, 21 CLKP, CLKN 22 OUTMODE 23 NAPSLP 25 RESETN 26, 45, 55, 65 OVSS 27, 36, 56 OVDD 32, 33 D0N, D0P [NC, D0] 34, 35 D1N, D1P [NC, D1] ...

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... KAD5512P-50 Pin Configuration AVDD 1 DNC 2 DNC 3 DNC 4 DNC 5 AVDD 6 AVSS 7 AVSS 8 VINN 9 VINP 10 AVSS 11 AVDD 12 DNC 13 DNC 14 VCM 15 CLKDIV 16 DNC 17 DNC 18 Rev 0.5.1 Preliminary KAD5512-50 72 QFN Top View Not to Scale Figure 3. Pin Configuration 54 D8P 53 D8N 52 D7P 51 D7N 50 D6P 49 D6N 48 CLKOUTP 47 CLKOUTN 46 RLVDS ...

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... KAD5512P-50 Typical Performance Curves All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, T +25 ° -1dBFS 500MSPS. IN SAMPLE 90 85 SFDR SNR 50 0 200 400 INPUT FREQUENCY (MHz) Figure 4. SNR & SFDR vs. f TBD Figure 6. SNR & SFDR vs. A TBD Figure 8. SNR & ...

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... KAD5512P-50 Typical Performance Curves TBD Figure 10. Power vs. f TBD Figure 12. Integral Nonlinearity TBD Figure 14. Noise Histogram Rev 0.5.1 SAMPLE Figure 15. Single Tone Spectrum @ 10 MHz TBD Figure 11. Differential Nonlinearity TBD Figure 13. SNR & SFDR vs. VCM TBD Page 11 ...

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... KAD5512P-50 Typical Performance Curves TBD Figure 16. Single Tone Spectrum @ 70 MHz TBD Figure 18. Single Tone Spectrum @ 240 MHz TBD Figure 20. Two-Tone Spectrum @ 10 MHz Rev 0.5.1 TBD Figure 17. Single Tone Spectrum @ 140 MHz TBD Figure 19. Single Tone Spectrum @ 500 MHz TBD Figure 21. Two-Tone Spectrum @ 70 MHz ...

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... KAD5512P-50 Typical Performance Curves TBD Figure 22. Two-Tone Spectrum @ 140 MHz TBD Figure 24. Two-Tone Spectrum @ 500 MHz TBD Figure 26. SNR & SFDR vs. Power Supply Voltage Rev 0.5.1 TBD Figure 23. Two-Tone Spectrum @ 240 MHz TBD Figure 25. SNR & SFDR vs. Temperature Page 13 ...

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... KAD5512P-50 Functional Description The KAD5512P-50 is based upon a 12-bit, 250MSPS A/D converter core that utilizes a pipelined succes- sive approximation architecture (Figure 27). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge domain techniques are used to successively compare the input to a series of reference charges. ...

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... VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differen- tial input resistance of the KAD5512P is 500º. The SHA design uses a switched capacitor input stage, which creates charge kick-back when the sampling capacitance is reconnected to the input voltage ...

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... KAD5512P-50 settling and improved performance. Therefore a 1:1 transformer and low shunt resistance are recom- mended for optimal performance. Figure 32. Differential Amplifier Input A differential amplifier, as shown in Figure 32, can be used in applications that require dc-coupling. In this configuration the amplifier will typically dominate the achievable SNR and distortion performance. ...

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... A 10kº, 1% resistor must be connected from the RLVDS pin to OVSS. Power Dissipation The power dissipated by the KAD5512P is primarily dependent on the sample rate, but is also related to the input signal in CMOS output mode. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate ...

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... KAD5512P-50 The power down mode can also be controlled through the SPI port, which overrides the NAPSLP pin setting. Details on this are contained in the Serial Pe- ripheral Interface section. This is an indexed function when controlled from the SPI, but a global function when driven from the pin. ...

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... SPI Physical Interface The SPI port operates in a half or full duplex mas- ter/slave configuration, with the KAD5512P-50 func- tioning as a slave. Multiple slave devices can inter- face to a single master. The chip-select bar (CSB) pin determines when a slave device is being addressed. ...

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... KAD5512P-50 [W1:W0] Bytes Transferred Table 6. Byte Transfer Selection Figures 42 and 43 illustrate the timing relationships for 2-byte and N-byte transfers, respectively. The opera- tion for a 3-byte transfer can be inferred from these diagrams. Rev 0.5.1 Preliminary Figure 41. Instruction/Address Phase Figure 42. 2-Byte Transfer x x Figure 43. N-Byte Transfer ...

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... KAD5512P-50 Setting this bit high resets all SPI registers to default values. Bit 4 Reserved This bit should always be set high. Bits 3:0 These bits should always mirror bits 4:7 to avoid ambiguity in bit ordering. Address 0x02: burst_end If a series of sequential registers are to be set, burst mode can improve throughput by eliminating redun- dant addressing ...

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... Address 0x73: output_mode_A The output_mode_A register controls the physical output format of the data, as well as the logical cod- 0x70[7:0] ing. The KAD5512P can present output data in two physical formats: LVDS or LVCMOS. Additionally, the drive strength in LVDS mode can be set high (3mA) or 256 low (2mA) ...

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... KAD5512P-50 overridden and controlled through the SPI, as shown in Table 14. This register is not changed by a Soft Reset. Value 000 001 010 100 Table 13. Output Mode Control Value 000 001 Two’s Complement 010 100 Table 14. Output Format Control Address 0x74: output_mode_B Address 0x75: config_status ...

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... KAD5512P-50 SPI Memory Map Addr (Hex) Parameter Name Bit 7 (MSB) 00 port_config SDO Active LSB First 01 reserved 02 burst_end 03-07 reserved 08 chip_id 09 chip_version 10 device_index_A 11-1F reserved 20 offset_coarse 21 offset_fine 22 gain_coarse 23 gain_medium 24 gain_fine 25 modes 26-5F reserved 60-6F reserved 70 skew_diff 71 phase_slip 72 clock_divide Output Mode [2:0] 73 output_mode_A 000=Pin Control 001=LVDS 2mA 010=LVDS 3mA ...

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... KAD5512P-50 Equivalent Circuits Figure 46. Analog Inputs AVDD CLKP AVDD 11k» 18k» 18k» AVDD 11k» CLKN Figure 47. Clock Inputs Figure 48. Tri-Level Digital Inputs Figure 49. Digital Inputs Rev 0.5.1 Preliminary AVDD To Charge Pipeline Layout Considerations Split Ground and Power Planes Data converters operating at high sampling frequen- cies require extra care in PC board layout ...

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... KAD5512P-50 Exposed Paddle The exposed paddle must be electrically connected to analog ground (AVSS) and should be connected to a large copper plane using numerous vias for opti- mal thermal performance. Bypass and Filtering Bulk capacitors should have low equivalent series re- sistance. Tantalum is a good choice. For best per- formance, keep ceramic bypass capacitors very close to device pins ...

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... KAD5512P-50 Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS signal amplitude to the RMS value of the peak spurious spectral component. The peak spuri- ous spectral component may or may not be a har- monic. Two-Tone SFDR is the ratio of the RMS value of the lowest power input tone to the RMS value of the peak spurious component, which may or may not be an IMD product ...

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... KAD5512P-50 Ordering Guide The KAD5512P-50 is compliant with EU directive 2002/95/EC regarding the Restriction of Hazardous Sub- stances (RoHS). Contact Kenet for a materials declaration for this product. Model KAD5512P-50Q72 Revision History 14-May-07: Rev 0.1 Updated to new format 21-Jun-07: Rev 0.2 Errata Updated 13-Aug-07: Rev 0.3 Content/specification updates 07-Dec-07: Rev 0 ...